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FPGA implementation method of SMV/GOose message based on rmii interface

An implementation method and interface technology, applied in the direction of synchronous signal speed/phase control, digital transmission system, data exchange network, etc., can solve the problems of increasing the cost of the merged unit, difficulty in hardware layout and wiring, and obstacles to the upgrade of the merged unit.

Active Publication Date: 2019-02-22
UNIV OF JINAN
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  • Abstract
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  • Claims
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Problems solved by technology

The traditional MII (Media Independent Interface, Media Independent Interface) interface has 16 pins. This interface can also realize the transmission of SMV / GOOSE, but it will increase the chip size and power consumption, and increase the PCB design. the complexity of
Seriously consumes the hardware resources of the FPGA, and brings considerable difficulties to the hardware layout and routing, which hinders the upgrade of the merging unit and increases the cost of the merging unit

Method used

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  • FPGA implementation method of SMV/GOose message based on rmii interface
  • FPGA implementation method of SMV/GOose message based on rmii interface
  • FPGA implementation method of SMV/GOose message based on rmii interface

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Embodiment Construction

[0031] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0032] Such as figure 1 As shown, the FPGA implementation method of the SMV / GOOSE message based on the RMII interface includes:

[0033] Step 1: Initialize the FPGA internal registers, buffer the message data to the sending buffer; wait for the sending enable signal;

[0034] Step 2: After receiving the enable signal, the transmit enable terminal TX_EN is pulled high to enter the data transmission state; whenever the PHY chip clock falls, 2-bit data is sent through the TXD[1:0] (transmit data line) port, and every time the When one byte is finished, the counter is incremented by one; firstly send 7 bytes of "0x55" (Preamble) for the receiver to realize synchronization and extract clock information, and then send 1 byte of "0xd5" (SFD) to use At the start of notifying the receiver of valid data;

[0035] Step 3: Send the message data in the buffer to ...

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Abstract

The present invention discloses an FPGA realization method of an SMV / GOOSE message based on an RMII. The method comprises a step 1 of initializing a register inside an FPGA, caching the message data to a sending buffer area, and waiting to send an enabling signal; a step 2 of after the enabling signal is received, pulling up a sending enabling terminal, firstly sending the lead data for a reception party to realize the synchronization and the clock information extraction, and then sending an SFD signal to notice the reception party the beginning of the effective data; a step 3 of sending the message data to a frame header part and an application protocol data unit orderly according to an SMV / GOOSE message frame format; a step 4 of when the message data reaches the length to be sent, ending the data transmission. According to the present invention, the transmission requirement of the instantaneous data is guaranteed, an SMV interface can externally transmit the waveform data efficiently and rapidly, the delay time of the data transmission can be reduced, and a GOOSE interface can guarantee the data transmission timeliness fully.

Description

technical field [0001] The invention relates to the field of power system data communication, in particular to an FPGA implementation method of RMII interface-based SMV / GOOSE messages. Background technique [0002] SMV is the abbreviation of Sampled Measured Value, sampling measurement value, also known as SV (Sampled Value), a communication service for real-time transmission of digital sampling information. The transmission of the sampled value (SMV) message at the data link layer is based on the Ethernet structure of IEEE802.3. [0003] GOOSE is the abbreviation of Generic Object Oriented Substation Event, a generic object-oriented substation event, which is the mechanism used in the IEC 61850 standard to meet the fast message requirements of the substation automation system. [0004] As the integration level of the Ethernet switch chip becomes higher and higher, the number of I / O port pins increases, and the power consumption also increases accordingly. The traditional ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L7/04H04L1/00H04L12/861
CPCH04L1/0061H04L7/041H04L49/9063
Inventor 程新功张浩于明珠丁冬睿李石清张静亮殷文月邵振振王玉真
Owner UNIV OF JINAN
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