Shift register, display substrate and display device

Abstract

The invention relates to a shift register. A shift register unit comprises a drop-down driving unit, a first drop-down unit, at least one second drop-down unit and at least one drop-down signal input end, wherein the drop-down driving unit is used for inputting a first drop-down signal to a drop-down node; the first drop-down unit is connected to the drop-down node, a pull-up node and a signal output end, and is used for denoising the pull-up node and / or the signal output end according to the first drop-down signal; the at least one drop-down signal input end is in one-to-one correspondence connection with the at least one second drop-down unit, and each second drop-down unit is connected to the pull-up node and the signal output end, and is used for denoising the pull-up node and / or the signal output end according to a second drop-down signal input by the correspondingly connected drop-down signal input end. By means of the technical scheme of the shift register, after the pull-up node realizes the pull-up function and the signal output end outputs the signal and before a first signal input end of the shift register unit receives a next high-level signal, the pull-up node at the output end can be continuously denoised, and accordingly, the denoisinig efficiency is improved.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to a shift register, a display substrate and a display device. Background technique [0002] The integrated gate shift register integrates the gate pulse output register on the panel, which saves IC and reduces the cost. There are many ways to realize this register, which can contain different numbers of transistors and capacitors. The commonly used structures are 12T1C, 9T1C, 13T1C and so on. The realization of the shift pulse must at least include a set of clock signals, a pull-up transistor, a pull-down transistor and an output transistor. [0003] Integrated gate shift registers are sensitive to noise. If the output noise of the current unit circuit cannot be effectively suppressed, it will be used as the input of the next unit to generate output, so that the noise is amplified step by step. Especially after working at high temperature for a period of time, this noi...

AI Technical Summary

Problems solved by technology

In the prior art, in order to use it, the discharge of the pull-down node PD is controlled by CLK. Only when CLK is at low level, the pull-down node PD is at high level, thereby reducing the noise of the signal output terminal OUT and the pull-up node PU. ; When CLK is at high level, it will make the pull-down node PD be at low level, so that the pull-down node PD cannot reduce the noise of the signal output terminal OUT and the pull-up node PU

Therefore, only during the time period when CLK is low level in one cycle, PD can realize the noise reduction function, but it cannot effectively reduce noise during the time period when CLK is high level.

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