Clock circuit used for high-speed high-precision SHA-less pipelined analog-to-digital converter

Abstract

The invention provides a clock circuit used for a high-speed high-precision SHA-less pipelined analog-to-digital converter. The clock circuit comprises first and second duty ratio stabilizing circuits and first to Nth output clock buffers. The first duty ratio stabilizing circuit generates a clock of which the duty ratio is adjustable and less than 50% and the clock is used for the first stage pipeline time sequence control. The second duty ratio stabilizing circuit generates a clock of which the duty ratio is 50% and the clock is used for the second stage to the Nth stage pipeline time sequence control. The first output clock buffer performs delay tuning on the clock outputted by the first duty ratio stabilizing circuit so as to realize time sequence alignment of the first stage pipeline and the subsequent stage pipeline. The second to the Nth output clock buffers drive the clock outputted by the second duty ratio stabilizing circuit. The two duty ratio stabilizing circuits are connected in series. Time sequence distribution of the first stage pipeline is enabled to be optimized by the clock of which the duty ratio is less than 50% so as to reduce the design difficulty of an operational amplifier, and the second to the Nth stage time sequences are enabled to be optimized by the clock of which the duty ratio is 50% so as to increase the reuse degree of the unit circuit.

Description

technical field [0001] The invention belongs to the technical field of clock circuits, and in particular relates to a clock circuit for a high-speed, high-precision pipeline-type analog-to-digital converter. Background technique [0002] The traditional pipelined analog-to-digital (A / D) converter structure is as follows: figure 1 As shown, the input signal is sampled using a sample-and-hold circuit (S / H), and the N-stage pipeline completes the step-by-step quantization of the input signal. The clock circuit generates the working sequence of the pipeline, such as figure 2 As shown, of course, because the control timing of the pipeline is very complicated, here we only focus on the main clock of each stage and ignore the non-overlapping time. Φ1p and Φ2p, Φ1n and Φ2n are two pairs of anti-phase clocks. During the high level period of the clock Φ1p, The odd-numbered pipeline stages are in the sampling phase, and at the same time, each sub-ADC in the odd-numbered stages perfo...

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Problems solved by technology

[0004] In the prior art, the sub-ADC of the first-stage pipeline does not quantize the input signal during the high level of Φ1p, but waits for the arrival of the high level of Φ1n before starting to work, thus greatly compressing the first-stage pipeline. Amplifying the phase time has caused the design of the operational amplifier in the first-stage pipeline to become very difficult, especially for the technical problems of high-speed and high-precision A / D converters. Clock circuit for converter

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