Single-event reinforced FPGA configuration circuit with code stream error detection and error correction function

Abstract

A single-event reinforced FPGA configuration circuit with the code stream error detection and error correction function comprises a bus interface circuit, a configuration bus, configuration registers, a coding error correction circuit and a configuration memory array.The bus interface circuit analyzes a configuration bit code stream to obtain configuration register addresses and internal data and transmits the configuration register addresses and the internal data to the corresponding configuration registers through the configuration bus, the configuration registers carry out read-write, configuration and error correction operation according to internal instruction words, the coding error correction circuit generates check codes after receiving configuration data words, transmits the check codes to the configuration memory array, reads the configuration data words and the check codes and carries out error correction, and the configuration memory array loads the configuration data words and the corresponding check codes.According to the single-event reinforced FPGA configuration circuit with the code stream error detection and error correction function, by additionally arranging the coding error correction circuit, the configuration data words in the configuration memory array can be read after configuration is finished for error detection and error correction, the problem that a logical error is likely to be introduced in an SRAM type FPGA chip in a space radiation environment due to single-event upset is solved, and the application value is high.

Description

technical field [0001] The invention relates to an FPGA configuration circuit, in particular to a single-particle reinforced FPGA configuration circuit with a code stream error correction and detection function. Background technique [0002] Such as figure 1 The field programmable gate array FPGA structure is shown, the input and output ports (IOB) are located around the chip, the configurable logic module (CLB) is arranged in an array internally, and the block memory (BRAM) is interspersed in the configurable logic module (CLB) ), FPGA also includes configuration logic, configuration interface and other components, such as programmable interconnect structure and configuration memory array (CSRAM) throughout the entire FPGA chip, connecting various modules. [0003] The SRAM type FPGA chip does not have any logic functions before configuration, and the function configuration is completed by loading the configuration data specified by the user application into the internal c...

AI Technical Summary

Problems solved by technology

[0004] When the FPGA chip is used in the space radiation environment, the space high-energy particles passing through the FPGA will cause an instantaneous current on the circuit node, causing the configuration storage unit SRAM in the configuration memory array to undergo a single-event flip, and the circuit in some areas will produce local functional errors. , short-circuit or disconnection of the interconnection wires, so that the circuit in this area cannot work normally, so a configuration circuit capable of checking and correcting the configuration memory array is required

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