SPARC V8 system structure based classified type mixed branch prediction system

Abstract

The invention discloses an SPARC V8 system structure based classified type mixed branch prediction system. Firstly, a branch target buffer is queried according to PC values of instructions at an instruction fetching stage to obtain branch instruction types; the branch instructions are dispatched to respective prediction modules; a return address stack (RAS) with a dynamic configuration counter is used in skip branch prediction; a complementary prediction method is used in indirect branch prediction; a tag recording correctness of previous branch prediction in a conditional branch target buffer (CBTB) adopts a partial skip three-state conversion algorithm in conditional branch prediction; decoding result information of the instructions are recorded in a prediction information table (PIT) at a decoding stage; a judgment is made at an execution stage; if a prediction result of the branch instructions is that the skip occurs, the result judgment is made by using a skip prediction result arbiter Arbiter_T; and if the prediction result of the branch instructions is that the skip does not occur, the result judgment is made by using a non-skip prediction result arbiter Arbiter_N. Therefore, the instruction delay influence of the branch instructions on an assembly line is eliminated and the execution efficiency of a processor is improved.

Description

technical field [0001] The present invention relates to a classification hybrid branch prediction system based on the SPARCV8 architecture, in particular, a classification hybrid branch prediction system based on the SPARCV8 architecture is provided for the widely used SPARC processor in the aerospace field, that is, the instruction classification method is adopted. hybrid branch prediction scheme. Background technique [0002] In the field of processors, the SPARC architecture, as one of the classic representatives of RISC processors, occupies a very important position. Microprocessors based on the SPARC architecture have good scalability and have been widely used in aviation, communications and various embedded applications. Therefore, the development of a SPARC processor with higher performance that can meet the application requirements of various target customers has a good application prospect. [0003] At present, the research on processor architecture has made great...

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Problems solved by technology

[0007] Branch prediction technology should not only consider its prediction accuracy, but also consider the hardware overhead and clock delay it brings to the processor. The existing branch prediction technology is often due to the large scale of hardware, the complexity of prediction algorithms, and the difficulty of branch prediction. Reasons such as low accuracy rate restrict the improvement of processor performance

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