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Soft-core CPU resetting method and master-slave type system

A reset method and soft-core technology, applied in the electronic field, can solve problems such as time-consuming and low efficiency

Inactive Publication Date: 2016-06-08
HUIZHOU WELLAV TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the traditional technology, the main CPU and the soft-core CPU communicate through the interface circuit to monitor the running status of the soft-core CPU. Once an abnormality occurs, the soft-core CPU is controlled to reset, that is, the main CPU initializes the configuration of the soft-core CPU. , and send the application program, this reset method, because the communication interface communication is usually slow, so the whole process takes a long time and the efficiency is relatively low. Slave devices may have caused huge problems

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  • Soft-core CPU resetting method and master-slave type system
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  • Soft-core CPU resetting method and master-slave type system

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Embodiment Construction

[0023] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0024] see figure 2 , providing a master-slave system, comprising a master CPU21, a system-on-chip and an off-chip RAM23, the system-on-chip comprising a soft-core CPU221, a boot program module 222, and a logic monitoring module 223;

[0025] The main CPU is configured to deliver the application program to the soft-core CPU;

[0026] The soft-core CPU is used to execute the boot program in the boot program module, and save the application program in the application program backup area and application program execution area in the off-chip RAM;

[0027] The soft-core CPU is also used to jump and ...

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Abstract

The invention discloses a soft-core CPU resetting method. The soft-core CPU resetting method comprises the steps that a master CPU sends application programs down to a soft-core CPU; the soft-core CPU executes a bootstrap program in a bootstrap program module and saves the application programs in an application program backup region and an application program execution region in an off-chip RAM; the soft-core CPU jumps to execute the application programs stored in the application program execution region on the basis of the bootstrap program and saves state parameters in a parameter save region in the off-chip RAM; a logic monitor module monitors the working state of the soft-core CPU and sends out a reset signal to the soft-core CPU when the logic monitor module detects that the soft-core CPU is abnormal; the soft-core CPU executes the bootstrap program to copy the application programs in the application program backup region to the application program execution region; the soft-core CPU jumps to execute the application programs stored in the application program execution region and reads the state parameters in the parameter save region, and therefore rapid resetting of the soft-core CPU is achieved. Compared with the prior art, the method has the advantages that the resetting efficiency of the soft-core CPU can be improved when the soft-core CPU is abnormal.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a method for resetting a soft-core CPU and a master-slave system. Background technique [0002] With the development of design and manufacturing technology, integrated circuit design has developed to the integration of IP, that is, SOC (System On-a-Chip) design technology. SOC can effectively reduce the development cost and shorten the development cycle, and is the most important product development method that the industry will adopt in the future. [0003] see figure 1 , is an application scenario of SOC in the traditional technology, and a master-slave system includes a master device 11 and a slave device 12 . The master device 11 has a master CPU, and the slave device 12 is implemented using an SOC. When the system is powered on, the main CPU performs initial configuration on the SOC and delivers the application program. One or more soft-core CPUs are used on the SOC ...

Claims

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Application Information

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IPC IPC(8): G06F11/07G06F11/14
CPCG06F11/0724G06F11/1438
Inventor 江锐唐受全
Owner HUIZHOU WELLAV TECH
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