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Multilevel boot method and system of digital signal processor

A digital signal and processor technology, applied in the field of digital signal processor multi-level start-up method and system, can solve the problems of multi-level start-up program without interrupt control system, unable to support embedded operating system and interrupt control system start at the same time, etc. achieve high portability

Inactive Publication Date: 2016-06-01
SPACE STAR TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical solution problem of the present invention is: to solve the deficiencies of the prior art, to provide a digital signal processor multi-level start-up method and system, to solve the problem that the existing Davinci architecture digital signal processor is not specially designed for multi-level start-up of the interrupt control system The program cannot support the start-up defect of the embedded operating system and the interrupt control system at the same time

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  • Multilevel boot method and system of digital signal processor
  • Multilevel boot method and system of digital signal processor
  • Multilevel boot method and system of digital signal processor

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Embodiment 1

[0053] The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings, see figure 1The flow chart of the multi-stage start-up method for a digital signal processor is shown, which includes the following steps:

[0054] S101, execute the first-level startup program of the digital signal processor, select the startup mode according to the peripheral configuration circuit, and read the second-level startup program;

[0055] S102, execute the start-up program located at the second level, complete the basic configuration of the minimum system of the digital signal processor, and jump to the third-level program stored in the external flash memory, and copy the third-level program in the external flash memory into memory;

[0056] S103. Execute the third-level program in memory.

[0057] The technical solution provided by this embodiment uses a multi-level boot program to start the third-level program stored in the ex...

Embodiment 2

[0070] In combination with the multi-stage startup method of the digital signal processor provided in the first embodiment, this embodiment also provides a method of how to write and burn the second-level startup program and the third-level program, so as to realize the multi-level startup of the digital signal processor , which, prior to execution of the first-level start-up procedure of the digital signal processor, may also include:

[0071] Write and compile the second-level startup program and the third-level program respectively, and convert the file format;

[0072] Burn the second-level startup program after the converted file format into the external EEPROM of the digital signal processor;

[0073] Burn the third-level program after the converted file format into the external flash memory.

[0074] see figure 2 As shown, it is one of the specific implementation methods, including the following steps:

[0075] Step S201, writing the second-level startup program, co...

Embodiment 3

[0096] On the basis of the above two embodiments, this embodiment further provides a typical method of executing the third-level program in memory to implement an interrupt control system on the basis of the multi-level startup method of the digital signal processor The method specifically includes the following steps:

[0097] The third-level program is executed sequentially from the entry address of the third-level program;

[0098] When an interrupt request occurs, the third-level program first turns to the first specified address to start running. The machine code of the preset byte starting from the first specified address is a short jump command, and a short jump address is specified. A long jump command and a long jump address are stored in the short jump address;

[0099] Execute the long jump command, store the interrupt detection function in the long jump address, judge the event that triggers the interrupt by reading the interrupt status register parameters, and re...

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Abstract

The invention provides a multilevel boot method and system of a digital signal processor. The method comprises following steps of executing the first-level boot program RBL (ROM boot loader) of the digital signal processor; selecting a boot mode according to a peripheral configuration circuit; reading a second-level boot program UBL (user boot loader); executing the second-level boot program UBL (user boot loader); finishing the basic configuration of the minimum system of the digital signal processor; skipping to a third-level program stored in an external flash memory (Nandflash); copying the third-level program stored in the external flash memory (Nandflash) to an internal memory; and executing the third-level program in the memory. According to the scheme of the invention, the third-level program stored in the external flash memory (Nandflash) of the digital processor is booted through a multi-level boot program mode; the third-level program may be an embedded operating system or an interrupt control system. According to the multilevel boot method of the digital signal processor, the multi-level boot program is designed aiming at the interrupt control system; an all-purpose universality solution is provided; and the boot of the embedded operating system and the interrupt control system can be supported at the same time.

Description

technical field [0001] The invention relates to the field of embedded development, in particular to a multi-stage startup method and system for a digital signal processor capable of simultaneously supporting an embedded operating system and an interrupt control system. Background technique [0002] Digital signal processors are used to measure or filter continuous analog signals, represent and process information digitally. The Davinci processor of Texas Instruments is a typical digital signal processor with a wide range of applications. It integrates a high-performance programmable core with memory and peripherals, including a programmable digital signal processor (Digital Signal Processor, DSP) , as well as video-oriented hardware accelerators, provide the required computing functions for real-time compression-decompression algorithms and other communication signal processing algorithms; the processor will also have a Reduced Instruction Set Computer (RISC) processor and a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/445
Inventor 刘朋樟余福荣张宏史培元胡宇齐跃震
Owner SPACE STAR TECH CO LTD
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