Three-dimensional semiconductor device and manufacturing method thereof

Abstract

A three-dimensional semiconductor device comprising a plurality of memory cells, each comprising: a channel layer distributed along a direction perpendicular to a substrate surface; a bottom gate conductive layer located in a first insulating layer stack and distributed on the side of the channel layer On the wall; the floating gate layer is located on the first insulating layer stack and distributed on the sidewall of the channel layer; a plurality of second insulating layers and a plurality of gate conductive layers are located on the floating gate layer and along the channel Layer sidewalls are stacked alternately; the gate dielectric layer is distributed on the sidewalls of the channel layer; the drain is located on the top of the channel layer; and the source is located in the substrate between two adjacent storage units of multiple storage units . The non-extracted floating gate is embedded inside, and the voltage is induced on the floating gate through the coupling of the voltage on the adjacent extraction gate to assist in completing the channel inversion of the contact area between the SEG and the polysilicon, thereby overcoming the current bottleneck in this area and increasing the channel current. Effectively control the threshold voltage consistency of the floating gate adjacent FETs.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a three-dimensional semiconductor storage device and a manufacturing method thereof. Background technique [0002] In order to improve the density of memory devices, the industry has made extensive efforts to develop methods of reducing the size of two-dimensionally arranged memory cells. As the size of memory cells in two-dimensional (2D) memory devices continues to shrink, signal collisions and interference can increase significantly, making it difficult to perform multi-level cell (MLC) operations. In order to overcome the limitations of 2D memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. [0003] Specifically, as figure 1 As shown, a multi-layer stack structure (for example, multiple ONO structures alternat...

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Problems solved by technology

In addition, the threshold voltage of the dummy cell will be due to the asymmetric fringe electric field (Fringe Field, such as figure 1 Arrow) will make the threshold voltage too large, difficult to control

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