Shift register unit, shift register and driving method of shift register

Abstract

The invention discloses a shifting registering unit, a shifting register and a driving method of the shifting register. One specific execution mode of the shifting registering unit comprises a first node controller, a second node controller, a third node controller and an output module. According to the execution mode, the situation that when the potential of the output end of the shifting registering unit is inverted, node potential completeness occurs to cause circuit malfunction can be avoided, meanwhile, the problem of suspension of circuit nodes is solved, and therefore the operating stability of a circuit is enhanced. The circuit is controlled to complete shifting of an input single pulse signal through two clock signals, power consumption is low, wiring is little, and design of a narrow frame is facilitated.

Description

Technical field [0001] This application relates to the field of display technology, and in particular to a shift register unit, a shift register, and a driving method of the shift register. Background technique [0002] In the design of the display panel, a shift register is usually used to output the shift signal row by row to turn on the thin film transistors connected to the gate line in a one-to-one correspondence, so that the data signal is written row by row into the pixel array to realize automatic row scanning of the display panel. . The shift register is generally formed by cascading multiple shift register units. The function of the shift register unit is to shift the input single pulse signal by one-half period before outputting. [0003] In the existing shift register unit design, generally more than two clock signals are used for control. figure 1 with figure 2 It is a schematic diagram of the circuit structure of two existing shift register units. Such as figure 1...

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Problems solved by technology

[0005] figure 2 for figure 1 The improved circuit designed for the node potential competition problem and the N12 node suspension problem in the shown circuit uses three clock signals CK1', CK2', CK3' for control, although the node potential competition and the N12 node suspension problem are avoided. The problem of circuit failure, but it needs to add a clock signal line, which is not conducive to the design of narrow borders, and increases power consumption

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