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Python language based Rapidio switcher logic simulation verification platform and method

A logic simulation and verification platform technology, applied in the field of cloud computing, to improve writing efficiency and reusability

Active Publication Date: 2015-10-07
SHANDONG LANGCHAO YUNTOU INFORMATION TECH CO LTD
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AI Technical Summary

Problems solved by technology

The UVM and SystemVerilog that appeared later provided convenience for verifiers to develop an object-oriented verification environment, but because SystemVerilog must be forward compatible with the classic Verilog syntax, its object-oriented mechanism has many inherent defects

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  • Python language based Rapidio switcher logic simulation verification platform and method
  • Python language based Rapidio switcher logic simulation verification platform and method

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Embodiment Construction

[0040] The present invention will be further described below in conjunction with specific embodiments by accompanying drawings of description:

[0041] A logic simulation and verification platform for Rapidio switchers based on the Python language. The verification platform includes: a SystemC interface function that interprets Python semantics, a DPI interface function that calls SystemVerilog from SystemC, a test case implemented by Python, and a running script.

[0042] The implementation steps of the verification platform are as follows:

[0043] 1) Instantiate the object under test of the Rapidio switch written in Verilog;

[0044] 2) Use Verilog program to write basic stimulus input and response output DPI functions to interact with the outer SystemC environment;

[0045] 3) Write a SystemC interpreter for Python;

[0046] 4) Write the underlying library functions of Python;

[0047] 5) Write Python test cases and run scripts.

[0048] The logic simulation verificati...

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Abstract

The present invention discloses a Python language based Rapidio switcher logic simulation verification platform and method. The verification platform comprises: a SystemC interface function for interpreting Python semantics, a DPI interface function used by SystemC to call SystemVerilog, and a test case and a running script realized by Python. According to the present invention, an interpreter between the Python language and the SystemC language is added, so that the Python language can directly control stimulus input of a logic simulator and compare responsive output and the test case programmed by using Python can be used directly in logic simulation and applied on a Rapidio switcher. By using the above environment, the programming efficiency and reusability of the test case can be greatly improved.

Description

technical field [0001] The invention relates to the technical field of cloud computing, in particular to a logic simulation verification platform and method for a Rapidio switch based on the Python language, and a method for performing logic simulation using the Python language. Background technique [0002] Chip logic function verification is an industry that continues to develop along with chip design, and function verification takes up the most time in the entire design cycle of a chip. While there are many techniques available to reduce verification time, there is no single verification method that is clearly applicable to a project. [0003] Traditional verification environments used in many SOC design projects with microprocessors are based on Verilog models and test vectors like C drivers. The C program simulates the start-up program of the microprocessor in the chip, reads and writes the registers of each component in the chip after startup, compares the actual regi...

Claims

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Application Information

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IPC IPC(8): G06F9/455
Inventor 耿介姜凯于治楼
Owner SHANDONG LANGCHAO YUNTOU INFORMATION TECH CO LTD
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