Multi-level collaborative and shared storage device and memory access method in gpdsp

Abstract

The invention discloses a GPDSP-oriented multi-level cooperative and shared storage device and a memory access method. The device includes a plurality of DSP cores and a global shared cache unit for caching off-chip storage data. Shared cache unit; each DSP core includes a parallel scalar storage unit and vector array storage unit, and each DSP core performs in-core data access through its own scalar storage unit and vector array storage unit, and shares data through the global shared cache unit ; The method uniformly addresses the scalar storage unit and the vector array storage unit, and configures the scalar storage unit to perform memory access according to the access data type. The invention can realize high-efficiency access and storage of data in a single core and efficient sharing of data between cores in the GPDSP, and has the advantages of high access efficiency, small hardware overhead and flexible configuration.

Description

technical field [0001] The present invention relates to the technical field of general-purpose digital signal processor (General-Purpose Digital Signal Processor, GPDSP), in particular to a storage device and memory access method for multi-level collaboration and sharing in GPDSP. Background technique [0002] As the development of integrated circuit technology is getting closer and closer to the physical limit of transistors, the method of improving the performance of microprocessors simply by increasing the main frequency will face an insurmountable power consumption wall, so microprocessors turn to monolithic integrated multi-core direction of development. As a high-performance multi-core general-purpose digital signal processor, GPDSP can efficiently realize a large number of digital signal processing in various embedded applications and general scientific computing applications, especially for a system with high data density, parallelism, and locality. Class applicatio...

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Problems solved by technology

[0004] 1) Due to the huge difference in the distance from the same microprocessor core to different memory banks, different data access delays are generated;

[0005] 2) Access to the same address space by multiple microprocessors may have different latencies;

[0006] 3) In a multi-core microprocessor, the cores are interconnected through an on-chip network. In addition to the length of the access distance, the memory access delay also depends on the bandwidth speed of the on-chip interconnection network, so the memory access delay is long and uncertain;

[0007] 4) Shared memory has become a data access bottleneck, requiring complex hardware structures to maintain data consistency in multi-core multi-level caches, which affects the scalability of multi-core shared storage

[0008] To sum up, the current distributed shared memory is not conducive to GPDSP's real-time and efficient digital signal processing, and it is difficult to exert its peak computing performance

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