Information security access architecture, method and system

Abstract

The invention provides an information security access architecture, method and system. The architecture comprises a CPU (central processing unit) chip, a plurality of PCIe (peripheral component interface express) exchanging chips and PCIe equipment; the CPU chip is respectively interconnected with the PCIe exchanging chips through a peripheral component express interconnection bus, i.e. a PCIe bus; the PCIe exchanging chips are interconnected with the PCIe equipment. By adopting the information security access architecture, method and system, the problem that the corresponding PCIe equipment cannot be accessed due to the failure of a communication link can be avoided, and the information security access is realized.

Description

technical field [0001] The invention belongs to the field of communication security control, and in particular relates to an information security access framework, method and system. Background technique [0002] At present, a CPU (Central Processing Unit, central processing unit) chip is interconnected with PCIe devices through the PCIe (Peripheral Component Interconnect Express, external device fast interconnection) bus. If a machine has multiple CPU chips interconnected, Each CPU chip is individually interconnected with the corresponding PCIe device through the PCIe bus. [0003] figure 1 Shown is the interconnection structure diagram of CPU chip and PCIe equipment in the prior art, as figure 1 Shown: The CPU chips are interconnected through the QPI (Quick Path Interconnect) bus for some data exchange, and each CPU chip will be individually interconnected with the corresponding PCIe device through the PCIe bus; but if one of the PCIe buses appears fault, the correspond...

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Problems solved by technology

[0003] figure 1 Shown is the interconnection structure diagram of CPU chip and PCIe equipment in the prior art, as figure 1 Shown: The CPU chips are interconnected through the QPI (Quick Path Interconnect) bus for some data exchange, and each CPU chip will be individually interconnected with the corresponding PCIe device through the PCIe bus; but if one of the PCIe buses appears fault, the corresponding PCIe device will not be able to be accessed normally, that is, the CPU chip connected to the faulty PCIe bus will not be able to normally access the corresponding PCIe device through the faulty PCIe bus, and data exchange will not be possible, causing certain security risks to communication

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