Chip package and manufacturing method thereof

Abstract

A wafer encapsulation, comprising a wafer (100) having an upper surface (100a), a lower surface (100b), and a side wall; the upper surface (100a) of the wafer (100) comprises a sensing area or an element area (200), and a signal receiving pad area (160); a shallow groove structure is located outside the signal receiving pad area (160), and extends from the upper surface (100a) towards the lower surface (100b) along the side wall; the shallow groove structure comprises at least one first notch (220) and one second notch (230) below the first notch (220); a rewiring layer (280) is electrically connected to the signal receiving pad area (160) and extends to the shallow groove structure; a wiring (440) has a first end point (440a) and a second end point (440b); the first end point (440a) is electrically connected to the rewiring layer (280) in the shallow groove structure; and the second end point (440b) is used for external electrical connection. The wafer encapsulation reduces the cladding thickness (H3) of an encapsulation layer (460) therein, increases the sensitivity of the sensing area (200), and maintains the structural strength of the substrate (150).

Description

technical field [0001] The present invention relates to a chip packaging technology, in particular to a chip package and a manufacturing method thereof. Background technique [0002] The chip packaging process is an important step in the process of forming electronic products. In addition to protecting the chip therein from external environmental pollution, the chip package also provides an electrical connection path between the electronic components inside the chip and the outside world. The manufacturing process of traditional chip packages involves multi-channel patterning process and material deposition process, which not only consumes production cost, but also requires a long process time. [0003] Therefore, it is necessary to find a novel chip package and its manufacturing method, which can solve or improve the above-mentioned problems, and provide a simpler and faster chip packaging technology. Contents of the invention [0004] An embodiment of the present inven...

AI Technical Summary

Problems solved by technology

The traditional chip package manufacturing process involves multi-channel patterning process and material deposition process, which not only consumes production cost, but also requires a long process time

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