A Fault Recovery Method Based on fpga

Abstract

The invention discloses an FPGA-based fault recovery method, which can monitor the working state of the FPGA after power-on, and reset the logic by using a hardware watchdog if the logic fails to be loaded successfully or the logic crashes. When the software embedded on the FPGA is unsuccessfully loaded or the software crashes, the software is reset through the logic watchdog to realize the fault recovery of the module without affecting the programming and configuration of the FPGA. The method is suitable for situations that require fault recovery, improves the reliability of work, and has general functions, which can be applied to various Xilinx FPGA-based fault recovery situations.

Description

technical field [0001] The invention relates to a fault recovery method based on FPGA. Background technique [0002] Xilinx's FPGA chip is a volatile device based on SRAM technology, and the circuit function is realized by data stored in SRAM configuration registers. After the FPGA chip is powered on, it must read the configuration information from the configuration FLASH before it can work normally. [0003] The FPGA configuration process includes 5 stages: initialization, clearing the configuration memory, loading configuration data, CRC check, START-UP, the power-on sequence of the configuration process is as follows figure 1 As shown, when the chip is powered on or the PROG_B signal of the FPGA is a low pulse, the configuration register will be cleared, that is, the configuration information will be read from the configuration FLASH again. The shortest pulse time of PROG_B is determined by T POR The time parameter determines that when the signal is valid (low level), ...

AI Technical Summary

Problems solved by technology

[0004] The existing FPGA is not equipped with a working status monitoring system. If an abnormal phenomenon occurs, it cannot be reset in time, and it also affects the programming and configuration of the FPGA.

Images