Shifting register and driving method thereof as well as grid electrode driving circuit and display device
A shift register and capacitor technology, applied in static memory, digital memory information, instruments, etc., can solve problems such as uneven horizontal bright lines and bright lines on the screen, inability to guarantee turn-off voltage, affecting display quality, etc. Interference, ensure display quality, and eliminate the effect of parasitic coupling effects
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Embodiment 1
[0045] An embodiment of the present invention provides a shift register 10, such as figure 1 As shown, the shift register 10 includes: an input module 11, which sends input to the output module 14, the reset module 12 and the maintenance module 13 according to the signal G input from the signal input terminal and the signal CK input from the first clock signal terminal. Signal; the reset module 12 is connected to the input module 11 and the signal output terminal, and resets the signal output terminal according to the signal CK input by the first clock signal terminal, the first level signal VL, the second level signal VH and the input signal; The maintenance module 13 is connected to the input module 11 and the output module 14, and sends to the output module 14 to eliminate the parasitic coupling effect according to the signal sent by the input module 11, the signal CB input by the second clock signal terminal, and the second level signal VH Affected maintenance signal; outp...
Embodiment 2
[0083] The embodiment of the present invention also provides a gate drive circuit, such as Figure 7 As shown, the gate drive circuit includes a plurality of cascaded shift registers 10 described in Embodiment 1, wherein the signal output terminals of each stage of shift register 10 are connected to a gate scanning line (Fig. not shown in ), and, except that the signal input end of the first stage shift register 10 inputs the start pulse signal, the signal input end of any stage shift register 10 is connected to the signal of the upper stage shift register 10 The output terminal, the signal output terminal of any stage shift register 10 is all connected to the signal input terminal of the next stage shift register 10;
[0084] The first clock signal terminal and the second clock signal terminal of any stage shift register 10 respectively input two mutually inverse clock signals (such as the first clock signal CK and the second clock signal CB). The first clock signal end...
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