A single-wire serial bus protocol and conversion circuit

Abstract

The invention discloses a single-line serial bus protocol and a conversion circuit, which are suitable for data transmission between chips. The inventive circuit interface includes: a clock signal terminal Clock, a set / reset signal terminal RS, a data input terminal D in , control signal terminal Ctr, data output terminal D out ; The circuit structure includes: five D flip-flops, three XOR gates, two AND gates, one OR gate, a multiplexer and two inverters. where, D flip-flop D 0 The data input terminal of the multiplexer is connected to the output terminal of the multiplexer; the D flip-flop D 1 、D 2 、D 3 、D 4 The output terminal Q is fed back to the D flip-flop D through a combinational logic circuit composed of an exclusive OR gate, an AND gate, and an inverter. 1 The input terminal D, according to the loop connection formed in this way, can be according to the data input terminal D in received data to control the data output D out High / low and duration of output level. The invention can convert the logic level into time-domain code, and reliably and asynchronously transmit data.

Description

technical field [0001] The invention belongs to the field of serial bus interface design, in particular to a single-line serial bus protocol and a conversion circuit. Background technique [0002] At present, the universal serial bus interface is widely used in various external devices, and it has the advantages of fast transmission speed, support for hot plugging and connection of multiple devices. However, this interface usually requires the use of both clock lines and data lines, which may cause asynchronous clock and data problems during transmission. In view of this, it is necessary to develop a single-wire serial bus protocol to transmit data asynchronously and reliably to solve the above problems. Contents of the invention [0003] The purpose of the present invention is to provide a single-wire serial bus protocol and a conversion circuit, which can convert logic levels into time-domain codes, thereby effectively improving the asynchronous problem of clock and dat...

AI Technical Summary

Problems solved by technology

However, this kind of interface usually requires the use of both clock lines and data lines, which may cause clock and data asynchronous problems during transmission.

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