Method for expanding memory, memory nodes, master node, and system

A technology for expanding memory and master nodes, applied in the directions of memory address/allocation/relocation, instrumentation, electrical digital data processing, etc., and can solve problems such as QPI bandwidth bottlenecks

Active Publication Date: 2013-08-14
HUAWEI TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

It can be seen that for the memory expansion board, due to the existence of multiple controller channels, the bandwidth of the QPI is a bottleneck

Method used

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  • Method for expanding memory, memory nodes, master node, and system
  • Method for expanding memory, memory nodes, master node, and system
  • Method for expanding memory, memory nodes, master node, and system

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Embodiment Construction

[0063] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0064] refer to figure 1 , figure 1 It is a system structure diagram of a first-level extended memory provided by the embodiment of the present invention. Such as figure 1 As shown, the system includes:

[0065] Grid (Grid), multi-level master nodes, QPI interface;

[0066] The Grid is configured to receive read and write request commands from other memory nodes and the master node in the same Grid; judge whether the other memory nodes and the master node acces...

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Abstract

An embodiment of the invention provides a method for expanding a memory, memory nodes, a master node, and a system. The method includes receiving read and write request commands of other memory nodes and the master node in a same Grid, determining whether the other memory nodes and the master node visit a same memory channel or not according to an address in the read and write request commands; if not, visiting a memory channel corresponding to an address according to the address in the read and write request commands sent by the other memory nodes and the master node, receiving returned data and ID (identifier) from the memory channel, and sending the data to other memory nodes or a master node corresponding to the ID. Thus, a function of memory expanding is realized, and topologies with different applications can be realized by utilizing an FPGA (field programmable gate array) and special integrated circuit chips according to designed memory capacity requirements.

Description

technical field [0001] The invention relates to the field of computer hardware, in particular to a method for expanding memory, a memory node, a master node and a system. Background technique [0002] In a computer system, the memory is one of the key factors determining the performance of the whole machine. With the rapid development of microelectronics technology, the performance of the processor has doubled, and the main frequency and bus bandwidth are very high, which requires the memory to provide a high data transfer rate to cooperate. Especially for multi-channel servers, there is an extremely high demand for storage capacity, and traditional storage access technologies can no longer meet the demand. Moreover, as the speed of the processor increases, the memory needs to provide more data to meet the requirements of the processor. However, it is quite difficult to increase the speed of the memory at present, which has caused the memory to become the biggest bottleneck...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16G06F12/08G06F3/06
Inventor 李涛常胜王工艺顾雄礼
Owner HUAWEI TECH CO LTD
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