Method for expanding memory, memory nodes, master node, and system
A technology for expanding memory and master nodes, applied in the directions of memory address/allocation/relocation, instrumentation, electrical digital data processing, etc., and can solve problems such as QPI bandwidth bottlenecks
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[0063] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
[0064] refer to figure 1 , figure 1 It is a system structure diagram of a first-level extended memory provided by the embodiment of the present invention. Such as figure 1 As shown, the system includes:
[0065] Grid (Grid), multi-level master nodes, QPI interface;
[0066] The Grid is configured to receive read and write request commands from other memory nodes and the master node in the same Grid; judge whether the other memory nodes and the master node acces...
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