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Method and device for optimizing mistake correcting mechanism

A mechanism and error technology, applied in the field of optimizing error correction mechanism, can solve the problems of unfavorable competition, large chip area and high cost, and achieve the effect of improving market competitiveness, optimizing working mode, and reducing the number of logic gates

Inactive Publication Date: 2013-06-26
SLICONGO MICROELECTRONICS INC
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Problems solved by technology

As the number of logic gates in flash memory (Flash) chips increases, if the corresponding logic optimization is not done, the area of ​​the chip will become larger and the cost will be higher and higher, which is not conducive to the market. compete

Method used

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  • Method and device for optimizing mistake correcting mechanism
  • Method and device for optimizing mistake correcting mechanism
  • Method and device for optimizing mistake correcting mechanism

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Embodiment Construction

[0032] The solution of the embodiment of the present invention is mainly to optimize the working mode of the error correction mechanism by allowing the encoding module and the syndrome calculation module in the error correction mechanism to share the same shift register according to different control signals, which not only ensures The error correction performance of the error correction mechanism is improved, and the number of logic gates of the error correction mechanism can be reduced.

[0033] Such as figure 1 As shown, a preferred embodiment of the present invention proposes a method for optimizing the error correction mechanism, including:

[0034] Step S101, the encoding module of the error correction mechanism encodes the original data through a shift register, and obtains the parity bit of the original data;

[0035] Assuming that the maximum error correction capability of the error correction mechanism is 30 bits, and under the Galois Field 13 domain, when the origi...

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Abstract

The invention discloses a method and a device for optimizing a mistake correcting mechanism. The method comprises the following steps: an encoding module of the mistake correcting mechanism encodes original data through a shifting register, and obtains an odd-even verification bit of the original data; and a correction sub-calculating module of the mistake correcting mechanism calculates the original data and the odd-even verification bit through the shifting register, and obtains a syndrome needed by the mistake correcting mechanism. According to the method and the device, by adopting the mode that the encoding module and the correction sub-calculating module in the mistake correcting mechanism share one same shifting register according to different control signals, the working mode of the mistake correcting mechanism is optimized, the mistake correction performance of the mistake correcting mechanism is ensured, and the logic gate count of the mistake correcting mechanism is reduced, so that the area and the design cost of a flash memory chip are reduced, and the market competitiveness of the flash memory chip is improved.

Description

technical field [0001] The invention relates to the technical field of flash memory, in particular to a method and device for optimizing an error correction mechanism. Background technique [0002] With the improvement of technology level, the capacity of flash memory (Flash) is getting larger and larger, but there will be a series of data stability problems. It is very important, and the greater the error correction capability of the error correction mechanism (ECC mechanism), the greater the consumption of hardware resources. The error correction mechanism (ECC mechanism) has 4 main modules: 1. Encoding module; 2. Correction Sub-computation module; 3. Calculation error polynomial module; 4. Correction module that solves the error position and corrects the error. As the number of logic gates in flash memory (Flash) chips increases, if the corresponding logic optimization is not done, the area of ​​the chip will become larger and the cost will be higher and higher, which is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42
Inventor 廖志雄
Owner SLICONGO MICROELECTRONICS INC
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