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Systems and methods for selective tungsten deposition in vias

A deposition cycle and metal deposition technology, which is applied to semiconductor devices, electrical components, circuits, etc., can solve the problems of tungsten grain growth limitation, limitation of tungsten filling amount, damage to perforation resistance, etc.

Active Publication Date: 2013-05-29
NOVELLUS SYSTEMS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The growth of the tungsten grains is restricted due to the dimensional contraction between the sides
As a result, the resistivity of the film is limited
At the same time, a gap is created in the middle of the hole, which limits the filling amount of tungsten and impairs the hole resistance.

Method used

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  • Systems and methods for selective tungsten deposition in vias
  • Systems and methods for selective tungsten deposition in vias
  • Systems and methods for selective tungsten deposition in vias

Examples

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Embodiment Construction

[0033] The following description is merely exemplary in nature and not limiting of the invention, its application or uses. For clarity of illustration, the same reference numerals will be used in the drawings to refer to similar elements. In this article, statements such as "at least one of A, B, and C" should be interpreted as the meaning of logic (A or B or C) using a non-exclusive logical "or". It should be understood that steps of a method may be executed in different order without altering the principles of the present invention.

[0034] The present invention utilizes metal selective growth, such as but not limited to chemical vapor deposition tungsten (CVD-W: chemical vapor deposition tungsten), to at least partially fill the vias using a bottom-up approach. This selective growth is followed by non-selective growth in the trenches and / or fields.

[0035] Metal selective growth such as but not limited to CVD-W, compared with interlayer dielectric (ILD: interlayer diele...

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Abstract

A method for processing a substrate includes providing a substrate including a metal layer, a dielectric layer arranged on the metal layer, and at least one of a via and a trench formed in the dielectric layer; depositing a metal using chemical vapor deposition (CVD) during a first deposition period, wherein the first deposition period is longer than a first nucleation period that is required to deposit the metal on the metal layer; stopping the first deposition period prior to a second nucleation delay period, wherein the second nucleation period is required to deposit the metal on the dielectric layer; performing the depositing and the stopping N times, where N is an integer greater than or equal to one; and after the performing, depositing the metal using CVD during a second deposition period that is longer than the second nucleation delay period.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of US Application No. 13 / 242,160, filed September 23, 2011, and US Provisional Application No. 61 / 386,791, filed September 27, 2010. The entire disclosure of the above application is hereby incorporated by reference in its entirety technical field [0003] The present application relates to systems and methods for bottom-up filling of vias using selective tungsten deposition. Background technique [0004] The background statement provided here for the purpose of generally presenting the subject matter of the invention, now referred to as the work of the inventors, is described in part in the background section, as with other aspects of the specification of the application, in the filing is not admitted to be prior art, nor is it expressly or implied to be prior art relative to the present invention. [0005] Semiconductor substrates often contain features such as through-holes fill...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/205H01L21/31
CPCH01L21/76877H01L21/76879H01L21/76876H01L21/28556
Inventor 高举文拉杰库马尔·亚卡拉朱迈克尔·达内克雷威
Owner NOVELLUS SYSTEMS
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