FPGA (field programmable gata array)-based clock data recovery processing method

Abstract

The invention provides an FPGA (field programmable gata array)-based clock data recovery processing method. The method can be realized by adopting an FPGA chip integrated with a CDR (clock and data recovery) artificial circuit. The method comprises the following steps of: firstly, carrying out clock data recovery with N frequency multiplication on input data by the CDR artificial circuit, so as to obtain real-time each-period frequency multiplication recovery data, and carrying out quick clock data recovery processing by using a means that the frequency multiplication recovery data are taken as oversampling data of input data. Therefore, not only can the problem of frequency limit as the digital oversampling is adopted in the prior art be solved, but also the problem that the accuracy can not be guaranteed until that the CDR artificial circuit needs longer-time recovery phase locking in the prior art can be solved, and the requirements of high-speed clock and quick recovery can be met, so that the burst type clock data recovery can be effectively realized by an FPGA chip designed by using the method, and the problem of the long-term dependency of a burst data communication system to a high-cost special BCDR (business continuity and disaster recovery) chip can be solved.

Description

technical field [0001] The invention relates to the technical field of communication data transmission, in particular to an FPGA-based clock data recovery processing method. Background technique [0002] In order to take advantage of the huge bandwidth of optical transmission, time-division multiplexing technology is often used in current communications to multiplex some low-speed signals onto a high-speed optical fiber. Due to the complexity of network synchronization, it is difficult to complete signals in different time periods There are always more or less differences in frequency and phase, which puts forward some special requirements for the clock and data recovery (CDR) at the receiving end. Especially in many communication services, it is often necessary to transmit some data with burst characteristics, which is called burst data (Burst Data). These burst data have the characteristics of random transmission time and short duration. Clock recovery for sending data re...

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Problems solved by technology

[0004] For the above-mentioned deficiency of prior art, the object of the present invention is to provide a kind of clock data recovery processing method based on FPGA, to solve the clock data recovery chip based on FPGA design in the prior art is difficult to meet the requirements of high-speed clock frequency and fast recovery at the same time However, it is difficult to apply to the problem of burst clock data recovery processing, so that the FPGA chip can also effectively realize the clock recovery of burst data

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