Circuit and method for correcting offset voltage of comparator

Abstract

The invention discloses a circuit and a method for correcting offset voltage of a comparator. The circuit for correcting the offset voltage of the comparator comprises the comparator, an output latch, a selecting module, a first substrate voltage generator and a second substrate voltage generator, wherein two input ends of the comparator are connected with working voltage or common mode level (VCM), a normal phase output end of the comparator is connected with the selecting module or a first output end (VOUT+) of the circuit of correcting the offset voltage of the comparator through the output latch, a reversal phase output end of the comparator is connected with the selecting module or a second output end (VOUT-) of the circuit of correcting the offset voltage of the comparator through the output latch, an input end of the first substrate voltage generator and an input end of the second substrate voltage generator are both connected with the selecting module, an output end of the first substrate voltage generator outputs a first variable voltage (VB+) to a metal oxide semiconductor (MOS) of a normal phase input end of the comparator and an output end of the second substrate voltage generator outputs a second variable voltage (VB+) to a metal oxide semiconductor (MOS) of a reversal phase input end of the comparator. The circuit for correcting the offset the voltage of the comparator and the method for correcting the offset voltage of the comparator has the advantages of being capable of rapidly achieving large-scale and high-precision correct because digital correction is applied and simultaneously correcting the substrate voltage of two input pipes, and more flexible.

Description

technical field [0001] The invention relates to the fields of analog circuits and digital circuits, in particular to a circuit and method for calibrating the offset voltage of a comparator. Background technique [0002] A comparator is a common module in analog integrated circuits and is widely used in analog-to-digital (A / D) and digital-to-analog (D / A) converters. The performance of the comparator greatly affects the performance of the system, but The performance of the comparator is severely restricted by its offset voltage, especially with the gradual reduction of the feature size of the CMOS process, the offset caused by the mismatch of the threshold voltage, area factor and parasitic capacitance gradually increases. [0003] Traditional offset voltage cancellation techniques, such as input offset storage (IOS) and output offset storage (OOS), use two-phase non-overlapping clocks and storage capacitors to eliminate offsets, which will introduce additional capacitance at ...

AI Technical Summary

Problems solved by technology

It should be pointed out that, first of all, the ladder resistance in this method will have static power consumption, and the additional bias voltage VDD / 2, V c The introduction of also increases the difficulty of wiring. Secondly, the use of counters greatly limits the calibration accuracy and calibration range, because the longest time required for an N-bit counter to find a suitable calibration voltage is 2 N clock cycle, considering the calibration efficiency, the counter takes up to 4 bits, which severely limits the range and accuracy of the calibrated offset voltage

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