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Method for implementing H.264 deblocking filter algorithm based on reconfigurable technique

A technology of deblocking filtering and implementation method, which is applied in the fields of digital video signal modification, electrical components, image communication, etc., and can solve the problems of complex operation, large amount of data, H.264 codec performance and flexible impact, etc.

Active Publication Date: 2014-04-16
SOUTHEAST UNIV
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Problems solved by technology

[0005] The problem to be solved by the present invention is: the deblocking filter algorithm in the existing H.264 decoding algorithm has a large amount of data and complex operations, which will affect the performance and flexibility of the H.264 codec

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  • Method for implementing H.264 deblocking filter algorithm based on reconfigurable technique

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Embodiment Construction

[0026] The method of the present invention aims at the deblocking filter algorithm in the H.264 decoding algorithm, removes the block effect brought by the transformation and quantization to the image, makes the block edge smooth, improves the visual effect, and at the same time, the filtered macro is used for inter-frame prediction and motion Compensation can obtain smaller residual data; this method is applied to a coarse-grained reconfigurable processor system, including the following steps: First, the algorithm needs to be divided into software and hardware and parallelism analysis to determine the data flow of the entire algorithm. Then it is necessary to optimize the algorithm and convert the source code to convert it into a form that can be realized by a reconfigurable array, mainly considering the implementation of the control flow; finally, convert the algorithm into a data flow graph form to generate the configuration information of the reconfigurable processing unit ...

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Abstract

The invention discloses a method for implementing H.264 deblocking filter algorithm based on a reconfigurable technique, which comprises the following steps: for a deblocking filter algorithm in an H.264 decoding algorithm, carrying out hardware / software division and parallelism analysis on the deblocking filter algorithm so as to determine a data flow circuit and a control flow circuit implemented by the whole algorithm; then, optimizing the algorithm, and carrying out source code conversion on the algorithm, so that the algorithm is converted into a form which can be implemented by a reconfigurable array; and finally, converting the algorithm into a data flow graph form, and generating the configuration information of a RPU (reconfigurable processing unit), thereby completing mapping. By using the method disclosed by the invention, a blocking effect on images caused by transformation and quantization is removed, so that the block edge is smooth, thereby improving the visual effect; meanwhile, through applying a macro-block subjected to filtering to inter-frame prediction and motion compensation, smaller residual error data can be obtained, therefore, due to an advantages of being applicable to vast parallelism computing tasks, the method can be applied to coarsness-reconfigurable processor systems.

Description

technical field [0001] The invention belongs to the field of embedded information technology, and is applied to the optimization of the H.264 decoding algorithm in the design of a high-performance embedded reconfigurable array system-on-chip SoC (system on chip) for media applications, and is a reconfigurable technology-based The implementation method of the H.264 deblocking filtering algorithm. Background technique [0002] Reconfigurable computing is a computing architecture that combines the flexibility of software and the efficiency of hardware. It has a good balance between key indicators such as performance, power consumption and flexibility, and fills the gap between general computing and Whitespace between dedicated calculations. The media processing technology based on reconfigurable arrays not only solves the key technologies of current graphics, image and video codec calculations, but also plays a pivotal role in future graphics, image and video codec calculation...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N19/117H04N19/176H04N19/80H04N19/86
Inventor 曹鹏范烨秋齐志王学香杨军
Owner SOUTHEAST UNIV
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