Dynamic voltage scaling system-oriented on-chip monitoring circuit

A technology of dynamic voltage regulation and monitoring circuit, which is applied in the direction of control/regulation system, regulation of electrical variables, and electrical digital data processing. Effects and other issues, to achieve the effect of timely and effective error recovery mode, switchable error recovery mode, and low power consumption

Active Publication Date: 2013-10-23
SOUTHEAST UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

System-level monitoring methods are mainly sensors, which can reflect the current working conditions of the system to a certain extent, but off-chip monitoring often depends on the accuracy of sensors, and it is difficult to choose reliable monitoring points, so it is difficult to truly reflect the internal status of each part of the chip. The actual situation
The method of inserting key units and duplicating key paths inside the chip can more truly reflect changes in the global parameters inside the chip. Changes in noise and process fluctuations are not sensitive, so they do not reflect the real situation of the circuit, which greatly affects the effect of voltage regulation

Method used

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  • Dynamic voltage scaling system-oriented on-chip monitoring circuit
  • Dynamic voltage scaling system-oriented on-chip monitoring circuit
  • Dynamic voltage scaling system-oriented on-chip monitoring circuit

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Embodiment

[0031] Example: see figure 1 and figure 2 , the present invention is oriented to an on-chip monitoring circuit for a dynamic voltage regulation system, comprising a main register circuit 1, a slave register circuit 2, a shadow register circuit 3, an error signal generating circuit 4, an in-situ error correction selector 5, and a metastable state monitoring circuit 6, Error signal integration circuit 7, recovery mode selection circuit 8 and in-situ error recovery control signal generation circuit 9 are nine sub-module circuits.

[0032]Working process of the present invention is as follows:

[0033] figure 2 Circuit diagram of transistor implementation for on-chip monitoring circuit with switchable error recovery mode. Among them, the complementary clock signal (clk_n, clk_p), the complementary in-situ error recovery control signal (restore_n, restore_p) and the complementary in-situ recovery circuit control signal (ctrl_n, ctrl_p) are respectively generated by two inverte...

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Abstract

The invention discloses a dynamic voltage scaling system-oriented on-chip monitoring circuit, which is characterized by comprising a master register circuit (1), a slave register circuit (2), a shadow register circuit (3), an error signal generation circuit (4), an in-situ error correction selector (5), a metastable state monitoring circuit (6), an error signal integration circuit (7), a restoration mode selection circuit (8) and an in-situ error restoration control signal generation circuit (9). By the dynamic voltage scaling system-oriented on-chip monitoring circuit, the influence of factors such as a process, voltage, temperature noise and the like on a main circuit can be effectively resolved into the variation of delay characteristics of a key unit and a special path to reflect the actual conditions of each part in a chip, and a dynamic voltage scaling effect is greatly improved.

Description

technical field [0001] The invention relates to an on-chip monitoring circuit, in particular to an on-chip monitoring circuit with a switchable error recovery mode for a dynamic voltage regulation system, belonging to the technical field of integrated circuits. Background technique [0002] As the size of the integrated circuit process shrinks further towards the ultra-deep submicron or even nanometer level, the power consumption per unit area of ​​the chip also increases exponentially, which makes power consumption an important factor that must be considered in addition to factors such as performance and area in integrated circuit design. question. Especially in recent years, with the increasingly widespread application of various battery-powered handheld devices and wireless sensor network node chips, various system chips have higher and higher requirements for low power consumption. How to minimize chip power consumption has become a Key problems to be solved urgently in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/00G05F1/569
Inventor 单伟伟朱肖顾昊琳刘超眭莉莉
Owner SOUTHEAST UNIV
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