Integrated logic analysis module based on PCIe (peripheral component interconnection express) for FPGA (field programmable gate array)

Abstract

An integrated logic analysis module based on PCIe (peripheral component interconnection express) for an FPGA (field programmable gate array), which comprises a trigger controller, a DMA (direct memory access) controller, a message transmitting engine, a message receiving engine and a PCIe receiving and transmitting controller. The integrated logic analysis module not only can realize all functions of SignalTap or Chipscope, but also can solve the problem of insufficient allowance of a Block RAM (random access memory) in a large-size design, and at the moment, as data are exported and stored in an internal memory of a CPU (central processing unit) side instead of being stored in a chip, sufficient data can be collected under permission of the internal memory. In addition, a trigger module is a register-level code, accordingly, more complicated triggering setting can be realized only by means of modifying the code, and the integrated logic analysis module is far more flexible than the SignalTap or the Chipscope. Besides, in the large-sized design, a CPU and an FPGA are commonly arranged in the same system, a PCIe link is a common channel of multiple high-speed systems, and accordingly the integrated logic analysis module is wide in application.

Description

technical field [0001] The invention relates to the field of FPGA development, in particular to the design and realization of high-efficiency chained DMA control data collection based on PCIe links, and in particular to a PCIe-based integrated logic analysis module for FPGA. [0002] Background technique [0003] At present, with the development of modern processor technology, it is a general trend to use high-speed differential buses instead of parallel buses in the field of interconnection. Compared with single-ended parallel signals, high-speed differential signals can use higher clock frequencies, thereby using fewer signal lines, and achieving bus bandwidths that previously required many single-ended parallel data signals. [0004] The PCI bus uses a parallel bus structure, and all external devices on the same bus share the bus bandwidth, while the PCIe bus uses a high-speed differential bus and adopts an end-to-end connection mode, so only two devices can be connected...

AI Technical Summary

Problems solved by technology

However, if you design with a logic analyzer, you need to pull the signal to a free pin, which is very inconvenient

If you use SignalTap or ChipScope, although you can easily collect the required signals, the two are limited to the remaining amount of BlockRAM inside the chip. Often, in large-scale designs, BlockRAM does not have enough margin for SignalTap or ChipScope. In this way, the amount of signals collected by the tool is very small, which cannot meet the needs in many cases.

Images