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PLL circuit for reducing reference leak and phase noise

A phase comparison circuit and circuit technology, applied in the direction of electrical components, automatic power control, etc., can solve problems such as dead zones, and achieve the effects of preventing phase errors, shortening locking time, and preventing output error phase errors

Inactive Publication Date: 2012-01-25
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0012] Furthermore, Patent Document 7 discloses a technology for stabilizing the operation by using a charge pump to perform only the charge and discharge required for the original phase difference between the reference signal and the comparison signal, but since it is necessary to set When the amount of delay is equal to or less than the dead zone width, and in the state where the compared phase coincides and is locked, neither charge current nor discharge current occurs as an error output, so there has always been a disadvantage of causing a dead zone.

Method used

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  • PLL circuit for reducing reference leak and phase noise
  • PLL circuit for reducing reference leak and phase noise
  • PLL circuit for reducing reference leak and phase noise

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Experimental program
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Effect test

Embodiment approach 1

[0084] exist figure 1 The structure of the PLL circuit in Embodiment 1 of the present invention is shown in . This PLL circuit includes a frequency-phase comparator 500 with a switching function, a charge pump 700 , a loop filter 750 , a voltage controlled oscillator (VCO) 800 , and a frequency divider 900 for dividing the output of the voltage controlled oscillator 800 .

[0085] The VCO 800 controls its oscillation frequency according to the voltage of the loop filter 750 , and the loop filter 750 charges and discharges the capacitors constituting the loop filter 750 through the output current of the charge pump 700 , and its voltage changes accordingly. The phase error output signal (UP signal and DN signal) output from the frequency-phase comparator 500 with switching function is input to the charge pump 700 , and a current corresponding to the phase error output signal is output. The frequency-phase comparator 500 with switching function inputs the reference signal FREF...

Embodiment approach 2

[0127] exist figure 2 A configuration diagram of a PLL circuit in Embodiment 2 of the present invention is shown in . In this embodiment, the same reference numerals are assigned to the same configurations as those in Embodiment 1, and description thereof will be omitted. In the PLL circuit of the present embodiment, instead of the frequency-phase comparator circuit 500 with a switching function in the PLL circuit of the first embodiment, a frequency-phase comparator 550 with a switching function provided with a reset input terminal is arranged.

[0128] exist Figure 5 Expressed in figure 2 The internal structure of the frequency-phase comparator 550 with switching function in the shown PLL circuit. Such as Figure 5 As shown, the frequency-phase comparator 550 of this embodiment is configured to input the reset signal NRST60 to the frequency comparison circuit 350 . exist Figure 11 Expressed in Figure 5 The internal structure of the frequency comparison circuit is...

Embodiment approach 3

[0137] exist image 3 A block diagram of a PLL circuit in Embodiment 3 of the present invention is shown in . In the present embodiment, the same reference numerals are assigned to the same configurations as those in the second embodiment, and description thereof will be omitted.

[0138] The PLL circuit in this embodiment differs from Embodiment 2 in that it includes a lock detection signal generator 600, and a frequency phase comparator 555 with a switching function generates a lock detection signal PLLLOCK in accordance with the comparison period signal WINDOW80 and the reference signal FREF10. .

[0139] exist Figure 6 said in image 3 The internal structure diagram of the frequency-phase comparison 555 with switching function in the PLL circuit shown. Such as Figure 6 As shown, the comparison period signal WINDOW is input as a data signal and the reference signal FREF10 is input as a clock signal to the lock detection signal generation unit 600 .

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Abstract

The present invention provides a PLL circuit for reducing reference leak and phase noise. A frequency / phase comparator having a switching function is configured to, based on a lock detection signal, switch between comparing frequencies by detecting rising edges of two signals to detect a phase difference between the two signals, and comparing phases by detecting voltage levels of the two signals to detect a phase difference between the two signals.

Description

technical field [0001] The present invention relates to a clock generating circuit such as a PLL circuit (Phase Locked Loop), and particularly relates to a technique for controlling a frequency-phase comparator according to the operating state of the PLL. Background technique [0002] Figure 13 A frequency-phase comparator 300 as a component in the conventional PLL circuit disclosed in Patent Document 1 is shown. [0003] exist Figure 13 Here, the reference signal FREF and the comparison signal FVCO are input to input terminals 10 and 20 , respectively, and are input to an edge comparator 50 via inverters 1 and 2 , respectively. The edge comparator 50 outputs a phase error output signal UP or DN corresponding to the comparison result of the reference signal FREF and the comparison signal FVCO to the respective output signal terminals 30 and 40 . [0004] In Patent Document 1, it is proposed that a Figure 13 In the frequency-phase comparator shown above, it is operated so...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/099H03L7/085
CPCH03L7/087
Inventor 衣笠教英千叶浩儿
Owner PANASONIC CORP
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