Exchange unit chip, router and transmission method of cell information

Abstract

The embodiment of the invention provides an exchange unit chip, a router and a transmission method of cell information. The exchange unit chip comprises a cell input module with multiple input ports, queue engine module and an cell output module with multiple output ports, wherein the cell input module buffers cell information received through each input port, assigns data cells in the cell information according to a corresponding assignment rule and transmits the data cells to the queue engine module according to an assignment result; the queue engine module comprises multiple independent data queue engine sub-modules, each data queue engine sub-module receives the data cells transmitted by the cell input module according to the corresponding assignment rule and stores the data cells in corresponding queues in each data queue engine sub-module; and the cell output module schedules the data cells according to a scheduling rule and sends the scheduled data cells out through the corresponding output ports. According to the embodiment of the invention, the exchange requirement of the Internet on higher flow can be met.

Description

technical field [0001] The embodiment of the present invention relates to data exchange technology, in particular to a method for sending exchange unit chip, router and cell information. Background technique [0002] At present, the switching unit of a large-capacity router mainly adopts a shared cache structure. All input and output ports access the same cache. In each clock cycle (Clock Cycle), all input and output ports can read and write at the same time, which greatly improves the performance of the switching unit. processing power. However, due to the limitation of the cache read-write cycle (Memory access cycle), the cell length (cell length) that an N-in N-out switching unit can process at line speed and its link speed (link speed) have the following relationship: Under the condition that the main frequency is 400MHz dual-port read and write processing, link speed is 10Gbps, and meets the pure 64Byte cell line speed, N<=20, that is, the number of physical connec...

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Problems solved by technology

[0004] In the process of realizing the present invention, the inventors have found that there are at least the following problems in the prior art: the prior art does not solve the problem essentially, but uses independent small units to piece together a switching unit, and all the small units are completely Similarly, it is not conducive to the expansion of the system in terms of resource utilization and unit splicing processing; moreover, because data cells need to be distributed to different small units, it also increases the cost of distribution flow sharing and rearrangement, and may also be caused by uneven distribution resulting in performance degradation

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