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Synchronization method and device of double 2-vote-2 system

A device, a technology for synchronizing interruption, applied in the direction of response error generation, redundancy in hardware for data error detection, instrumentation, etc., to eliminate timing errors, avoid potential errors or dangerous actions, and avoid common mode errors.

Active Publication Date: 2010-11-03
CRSC RESEARCH & DESIGN INSTITUTE GROUP CO LTD
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Problems solved by technology

[0004] However, since there are a large number of security control and measurement tasks based on clock sources in railway signal control, the comparison method based on the same clock of two times two out of two cannot avoid the common mode error caused by the common clock source; in addition, due to This bus-level synchronization method must perform a two-by-two comparison in the same software environment, which cannot avoid potential safety hazards caused by the same specific software and its specific implementation method.

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Embodiment Construction

[0034] CPLD: Complex Programmable Logic Device, complex programmable logic device.

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0036] The core of the present invention is: there are two identical departments in the system, and the two CPUs performing the same action in each department are all equipped with internal timers, as timing clocks for performing tasks, and the two CPUs perform tasks through the communication unit in the department. Communicate and execute reset instructions through connected timer...

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Abstract

The embodiment of the invention discloses a synchronization method of a double 2-vote-2 system, the system has two same systems, two CPUs with same actions in each system are both provided with an internal timer as a timing clock when performing a task, and the two CPUs communicate through a communication unit in the systems, execute a reset instruction through the connected timers respectively and control the synchronization of the two CPUs in the systems in combination with a common clock source which can generate high-frequency pulse signals; and simultaneously, the two systems communicate with each other, CPU synchronization data of a main system is transmitted to a subordinate system, thus carrying out synchronization control between the main system and the subordinate system. The invention also discloses a device corresponding to the method. As each CPU in the system has the independent internal timers and each system has an external timer, through the coordination, a common-mode error caused by sharing a clock in the prior art is effectively avoided, and the two CPUs in the systems can realize the diversity of the hardware with the same function by adopting different software.

Description

technical field [0001] The invention relates to the technical field of railway signals, and more specifically, to a synchronization method and equipment for a two-by-two system. Background technique [0002] The railway signal control system completes the control functions of related signal equipment, and adopts a two-by-two system with better performance. The system is composed of two identical safety control systems. Under the premise of synchronization, it is used as a hot backup to ensure that in the case of a single system failure, the normal work process can be completed through the master-slave system switching. In the two-by-two system, the CPUs in the two systems need to work synchronously to ensure normal operation. Therefore, a reasonable and reliable CPU synchronization method for the two-by-two system is particularly important. [0003] The more commonly used method in the current two-by-two system is the bus-level synchronization method, that is, the two CPUs ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/16G06F13/24
Inventor 张利峰邱兆阳孙寿龙赵晓东周夏芳崔新民张乐平佘晓丽李民陈强卢利勇于长洪
Owner CRSC RESEARCH & DESIGN INSTITUTE GROUP CO LTD
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