Synchronization method and device of double 2-vote-2 system
A device, a technology for synchronizing interruption, applied in the direction of response error generation, redundancy in hardware for data error detection, instrumentation, etc., to eliminate timing errors, avoid potential errors or dangerous actions, and avoid common mode errors.
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[0034] CPLD: Complex Programmable Logic Device, complex programmable logic device.
[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.
[0036] The core of the present invention is: there are two identical departments in the system, and the two CPUs performing the same action in each department are all equipped with internal timers, as timing clocks for performing tasks, and the two CPUs perform tasks through the communication unit in the department. Communicate and execute reset instructions through connected timer...
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