High-speed multi-channel clock data recovery circuit

Abstract

The invention discloses a high-speed multi-channel clock data recovery circuit. The circuit comprises: an oversampling frequency discriminator which is used for receiving a reference clock, and outputting a digital signal after frequency discrimination; a digital filter which is used for receiving and processing the digital signal, and then outputting a comparing control signal; a distributed oscillator which is used for receiving the comparing control signal and generating a high-speed clock signal; a first frequency divider and a second frequency divider which are used for receiving the high-speed clock signal, wherein, an obtained result is transmitted to the oversampling frequency discriminator after the high-speed clock signal is processed by the first frequency divider, and a clock signal which is needed in an operation performed by the digital filter is generated after the high-speed clock signal is processed by the second frequency divider; a delay loop which is used for receiving the high-speed clock signal and generating n pairs of clock signals; and n oversampling data clock generators each of which receives a pair of clock signals output by the delay loop and one channel of high-speed data corresponding to the pair of the clock signals, and processes and recovers the clock signals and the high-speed data corresponding to the clock signals. The high-speed multi-channel clock data recovery circuit has the advantages of strong programmability and wide adaptability.

Description

technical field [0001] The invention belongs to the field of microelectronic circuits, in particular to a high-speed multi-channel clock data recovery (CDR, Clock and Data Recovery) circuit. Background technique [0002] In the design of electronic circuits, data transmission and reception are usually transmitted at high speed through optical fibers or backplanes or between chips, while the processed data is usually relatively low-speed, so a large number of SERDES (serial-to-parallel conversion circuits) are required for serial-parallel Conversion and parallel-to-serial conversion, in which the design and application of the CDR circuit is very critical. The CDR circuit recovers the clock in the transmitted serial high-speed data and extracts the data, and then converts it into low-speed parallel data as needed. [0003] Traditional high-speed (set to high-speed at frequencies exceeding 1Ghz) CDR circuits include frequency detectors, phase detectors, charge pumps, filters, ...

AI Technical Summary

Problems solved by technology

[0008] In view of the above-mentioned shortcomings, the purpose of the present invention is to provide a high-speed multi-channel clock data recovery circuit, which effectively solves the problem of narrow tuning range in the prior art and is not suitable for high-speed transmission of multi-phase signals

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