Efficacy push-pull buffer circuit, system and method for high frequency signals

Abstract

The invention relates to an efficacy push-pull buffer circuit, a system and a method for high frequency signals. The buffer circuit comprises a biasing circuit which can be operated to generate a first bias signal and a second bias signal. A capacitance network comprises an input end suitable for receiving input signals and can be operated to respond to the input signal so as to generate a first bootstrapping signal and a second bootstrapping signal. A push-pull stage comprises a first control input end, a first control output end, a second control input end and a second control output end. The push-pull stage is coupled to the biasing circuit to receive the first and the second bias signals at the first and the second control input ends respectively, and is also coupled the capacitance network to receive the first and the second bootstrapping signals at the first and the second control output ends respectively. The push-pull stage can be operated to respond to the first and the second bootstrapping signals so as to generate buffer output signals at the output ends.

Description

technical field [0001] [1] Embodiments of the present invention generally relate to buffer circuits, and more particularly, to push-pull buffer circuits, systems and methods for high frequency signals. technical background [0002] [2] Many electronic systems use high-frequency signals, such as clock signals, that must be supplied to a large number of components within the system. In these cases, buffer circuits are often required to adequately drive the large number of components that receive the clock signal and to isolate the circuit that generates the high-frequency clock signal, such as a crystal oscillator, from the large number of components. This isolation is necessary so that the circuits generating the high-frequency clock signal are not unduly loaded by these components, which would cause unwanted variations in the high-frequency clock signal, such as in the frequency, amplitude and phase of the clock signal changes in . [0003] 【3】 figure 1 shows a convention...

AI Technical Summary

Problems solved by technology

Using source follower 400, the voltage swing of the BCLK signal is limited by the gate-source voltage Vgs of NMOS transistor 402, and if the lowest level of the CLK signal is less than this gate-source voltage, the buffer clock signal is clipped

As the magnitude of the supply voltage Vdd decreases, the gate-source voltage Vgs of the NMOS transistor 402 becomes a significant impediment to the proper operation of the source follower 400

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