Efficient execution of memory barrier bus commands

A technology of memory and memory controller, applied in the direction of concurrent instruction execution, machine execution device, instrument, etc.

Active Publication Date: 2009-03-25
QUALCOMM INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, the next memory operation after the memory barrier is delayed until eve...

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  • Efficient execution of memory barrier bus commands
  • Efficient execution of memory barrier bus commands
  • Efficient execution of memory barrier bus commands

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Embodiment Construction

[0018] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various embodiments of the invention and is not intended to represent the only embodiments in which the invention may be practiced. The detailed description contains specific details for the purpose of providing a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the invention.

[0019] figure 1 is a conceptual block diagram illustrating an example of a weakly ordered processing system. Processing system 100 may be a computer, be resident in a computer, or any other system capable of processing, retrieving and storing information. Processing system 100 may be a stand-alone system or, alternatively, ...

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Abstract

The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being producedbefore the execution of all memory access requests issued by the master device to the memory before the memory barrier.

Description

[0001] Related Application Cross-References [0002] This patent application claims priority to Provisional Application No. 60 / 781,091, filed March 10, 2006, entitled "Efficient Execution of Memory Barrier Bus Commands," and states The provisional application is assigned to its assignee and is expressly incorporated herein by reference. technical field [0003] The present invention relates generally to processing systems, and more particularly, to techniques for efficiently processing memory barrier bus commands in a processing system. Background technique [0004] Computers and other modern processing systems have revolutionized the electronics industry by enabling complex tasks to be performed with just a few keystrokes. These complex tasks often involve several devices that communicate with each other using a bus in a fast and efficient manner. The bus provides a shared communication link between devices in the processing system. [0005] Depending on the particular ...

Claims

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Application Information

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IPC IPC(8): G06F9/38
CPCG06F13/1621G06F9/522G06F9/52G06F13/16G06F9/38
Inventor 詹姆斯·爱德华·小沙利文贾亚·普拉喀什·苏布拉马尼亚姆·贾纳桑理查德·爱拉尔德·霍夫曼
Owner QUALCOMM INC
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