Processor, test tray transfer method and package chip manufacture method
A technology for testing trays and installing chips, which is applied in the field of processors and can solve problems such as control operation errors
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[0040] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
[0041] image 3 It is a plan view of the structure of the processor used in the present invention. Figure 4 is a schematic diagram of the test tray path between the loading unit and the unloading unit in the handler. Figure 5 is a schematic diagram of the path of the test tray inside the chamber of the first embodiment of the present invention. Image 6 is a schematic diagram of the path of the test tray inside the chamber of the second embodiment of the present invention. Figure 7 is a plan view of the handler illustrating the path along which the test tray is moved from the unloading position to the loading position.
[0042] like image 3 As shown, the handler 1 of the present invention includes a loading stacker 2, an unloading stacker 3, a loading unit 4, an unloading unit 5, a rotating unit 6, a picker...
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