Double-sampling full-difference sampling-hold circuit

Abstract

The invention relates to the technical field of a sampling hold circuit in a pipeline analog-to-digital converter and discloses a double-sampling and fully-differential sampling hold circuit which comprises a first differential switched capacitor unit, a second differential switched capacitor unit and a double-folding branch operational amplifier, wherein, the first differential switched capacitor unit and the double-folding branch operational amplifier samples in high-time state at clock signals ph1 and phs and keeps in the high-time state at the clock signal ph2; and the second differential switched capacitor unit and the double-folding branch operational amplifier samples in the high-time state at the clock signals ph2 and phs and keeps in the high-time state at the clock signal ph1. By utilizing the sampling hold circuit of the invention, the output DC offset caused by the out-of-control of the operational amplifier is reduced, the accuracy of the sampling hold circuit is improved and the set-up speed of the sampling control circuit in a hold phase is improved.

Description

technical field [0001] The invention relates to the technical field of sampling and holding circuits in pipeline analog-to-digital converters (ADC), in particular to a double-sampling fully differential sampling and holding circuit. Background technique [0002] Sampling and holding circuit (SHC) is an important part of many analog-to-digital converters, such as pipelined analog-to-digital converters, and its speed and accuracy determine the performance of the entire ADC. The double-sampling sample-and-hold circuit is a commonly used high-speed sample-and-hold circuit. It outputs effective hold voltages in both phases of the two-phase non-overlapping clock. Under the premise of applying the same operational amplifier, the speed is as fast as the traditional sample-and-hold circuit ( Only in the hold phase output effective hold voltage) nearly twice. [0003] Traditional double-sampling sample-and-hold circuits such as figure 1 As shown, the sample-and-hold circuit is contr...

AI Technical Summary

Problems solved by technology

[0008] First of all, there is an offset voltage in the op amp, which is added to the output of the op amp, which makes the output voltage of the sample and hold circuit have a DC offset

[0009] Secondly, the parasitic capacitance at the input end of the op amp will save the information of the previous phase. When the gain and bandwidth of the op amp are relatively large, the parasitic capacitance at the input end of the op amp is very large, which seriously affects the accuracy of the sample and hold circuit.

[0010] In addition, when the op amp is in the hold phase, the on-resistance of the switch in series with the input affects the speed at which the op amp settles

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