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Universal asynchronous serial extended chip of multi-bus interface

A universal asynchronous and serial port expansion technology, which is applied in the field of universal asynchronous serial port expansion chips with multi-bus interfaces, can solve the problems of slow communication speed, complicated operation and high cost, and achieve the effect of reducing the burden

Inactive Publication Date: 2008-02-20
CHENGDU WEIKAI MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Up to now, there are more than 40 kinds of UART devices to choose from around the world, but because multiple UARTs work at the same time involves relatively complicated internal timing and cooperative work processing, the current UARTs are still very versatile, pins, and registers until today. There are few changes, and there are only a handful of UART extensions that can truly achieve full functions
Most UART devices are based on the computer bus conversion UART, which generally has the disadvantages of complex operation, many pins, and high cost.
[0006] In embedded applications, the microprocessor controller MCU and peripherals basically use serial ports for communication, and most microprocessor controllers MCU only have one serial port. Traditional serial port expansion ICs generally need to occupy a large number of IOs of the MCU. Suitable for use in embedded systems
Now, more software is used to simulate the serial port, which has the disadvantages of occupying MCU resources, slow communication speed, and unreliable communication.

Method used

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  • Universal asynchronous serial extended chip of multi-bus interface
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  • Universal asynchronous serial extended chip of multi-bus interface

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0048] As shown in Figure 1, a universal asynchronous serial port expansion chip with multiple bus interfaces includes a host interface, a sub-channel processing module, a MODEM control logic module, an interrupt control logic module, and a clock generator. The host interface includes an 8-bit parallel bus. Interface, serial peripheral interface SPI bus interface, UART bus interface, internal integrated circuit bus I 2 C bus interface, protocol processor, global register, and mode selection control logic module; the four bus interfaces are all connected to the CPU / DSP host, the bus type corresponding to the host is selected through the bus processing logic, and the SPI, SPI, and SPI are processed through the bus processing logic. UART, I 2 The unified conversion of the data and data format of C and 8-bit parallel buses; the global register setting sets the working state of the chip host interface; the mode selection control logic module selects the host interface through the mode ...

Embodiment 2

[0061] A universal asynchronous serial port expansion chip with multi-bus interface. This chip adopts a simplified register structure. The register is numbered according to the address as a 6-bit address number, and the address is 000000~111111.

[0062] The host interface of the chip includes RSV, global control register GCR, global main serial port control register GMUCR, global interrupt register GIR, global XOFF character register GXOFFH and global XON character register GXON, a total of 6 global registers.

[0063] The address of the global register is XX0000-XX0101, where XX is any one of 00, 01, 10, 11, the upper 2 bits are the channel number, the lower 4 bits are the register address number, and the lower 4 bits of the address are arranged in detail See the table below:

[0064] The global register list is as follows:

[0065] Register address[3:0]

Register name

Types of

Register function description

(XX)0000

RSV

No

Keep

(XX)...

Embodiment 3

[0109]The chip in the present invention supports a data broadcast mode in which the sub-serial channel can be independently configured. By setting the GBDEN bit in the global register GCR, the global broadcast of the master port is set to enable, and then the RDBEN bit of the SCTLR of the corresponding sub serial channel that needs to receive broadcast data is set, so that the channel can receive data broadcast. After the main interface control logic detects the broadcast setting, it sends the data of the main port to all the sub-serial ports. The broadcast data can be set to receive the sub-serial port that is enabled to receive the broadcast, but the sub-serial port that is not set to receive data broadcast will ignore the data. . So as to realize the data broadcasting function that can be independently configured.

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PUM

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Abstract

The utility model discloses a multi-bus interface extended chip with general asynchronous serial ports, comprising a host interface, a subchannel processing module, a MODEM control logic module, an interrupt control logic module and a clock generator. The utility model is characterized in that the host interface comprises a 8-bit parallel bus interface, a serial peripheral interface SPI bus interface, a UART bus interface, an internal integrated circuit bus I2C bus interface, a protocol processor, a global register and a mode selection control logic module, wherein the four bus interfaces are all connected with the CPU / DSP host and the bus type corresponding the host is selected through the bus processing logic, in addition, the data and the conversion of data format are processed through the bus processing logic. The working state of the host interface of the chip is setup by the global register and the mode selection, the mode selection control logic module selects the host interface and the signal line through mode. The utility model supports 8-bit parallel bus, SPI bus, I2C, UART and other host bus interfaces, realizes a plurality of extended serial ports for buses, besides, the utility model has compact and perfect configuration register structure and enables multi-working modes set of the sub serial ports independently, and supports high-speed communication, and each channel has independent and controllable data broadcasting and receiving function, and all UARTs support IRDA infrared communication.

Description

Technical field [0001] The invention relates to a UART universal asynchronous serial port expansion integrated circuit chip, in particular to a universal asynchronous serial port expansion chip with a multi-bus host interface, the sub-channels can be independently set, and a built-in multi-bus protocol processor and a simplified register structure. Background technique [0002] The Universal Asynchronous Receiver / Transmitter (Universal Asynchronous Receiver / Transmitter) was born in the 1970s and is currently widely used in computers, communications, industrial control, household appliances, consumer electronics and other fields. UART is the first large-scale integrated circuit. UART has been produced a few years before the appearance of monolithic microprocessor. Compared with 30 years ago, the structure of current UART is basically similar. [0003] As a universal serial data bus, UART is mainly used for asynchronous communication. This bus has two-way communication and can real...

Claims

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Application Information

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IPC IPC(8): G06F13/40
Inventor 赵广宇杨国政陈谦贺大庆张建峰
Owner CHENGDU WEIKAI MICROELECTRONICS CO LTD
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