Non-volatile memory device and method of handling a datum read from a memory cell

Abstract

Memory devices that include a pre-charge transistor for connecting / disconnecting the input line of the global data line driver to a supply voltage line are more power consuming than the memory devices that do not include it because of a small though significant flow of current through the pre-charge transistor even in stand-by state. This problem is solved with a method implemented in a novel memory device, by turning on the pre-charge transistor only when, at the same time, the enabling signal of the page buffer is asserted, a low voltage functioning mode is selected and the memory device is not in a stand-by state, or the memory device is in a stand-by state but the datum read from the memory is high. The pre-charge transistor is securely turned off in all other cases.

Description

technical field [0001] The present invention relates to memory devices, and more particularly to memory devices including a global data line driver with an improved architecture to prevent errors in transferring read data to global data lines of the memory device. Background technique [0002] A non-volatile memory device organized and operating in a so-called page mode includes circuitry called a "page buffer" dedicated to storing data to be programmed at The data to be read from the addressed location of the cell array. The page buffer includes a data driver for each memory cell of a page for outputting read data. [0003] To understand the operation of the page buffer during a read operation, we refer to the classical scheme of Figure 1. Basically, during each read operation, when the enable signal PBDO is asserted, the data driver of the page buffer (PAGE BUFFER) transfers the data DATA read from each memory unit to the buffer output node. [0004] The output of the ...

AI Technical Summary

Problems solved by technology

[0009] Unfortunately, it has been found that memory devices incorporating the circuit of Figure 2 consume more power than memory devices incorporating the circuit of Figure 1

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