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A method for realizing SDH adaptation to Ethernet rate with logic

A rate adaptation, Ethernet technology, applied in the field of microelectronics, can solve problems such as low efficiency, low RAM access efficiency, and no burst read and write method, so as to improve access efficiency, reduce waiting time, and improve efficiency Effect

Inactive Publication Date: 2008-01-09
CHIPHOMER TECH SHANGHAI
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  • Summary
  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0006] 1. The adaptation of multiple SDH cascaded data channels to a single Ethernet port is not realized;
[0007] 2. When using off-chip RAM, the channel average round-robin mechanism is used, resulting in low efficiency
[0008] When using off-chip RAM, the burst read and write method is not used, resulting in low RAM access efficiency

Method used

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  • A method for realizing SDH adaptation to Ethernet rate with logic
  • A method for realizing SDH adaptation to Ethernet rate with logic

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Embodiment Construction

[0025] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0026] As shown in Figures 1 and 2, in the front-end functional modules, the analysis of SDH data frames and the analysis of encapsulation protocols (such as GFP protocol or HDLC protocol) have been realized. Each input channel will have an independent IB (input buffer). Each IB is composed of 4 BLOCKs. Each BLOCK can store 64 bytes of data. The input data is first stored in the on-chip IB. Every once in a while, through the priority weighting principle mentioned above, one of the multiple channels with data stored in the IB will be selected, and the data in a BLOCK in this channel will be sent to the off-chip RAM.

[0027] The output data is sent to the back-end module, and then sent to the MAC port after certain protocol processing and framing operations. Each output channel will have an independent OB (output buffer). Each OB cons...

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PUM

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Abstract

The method comprises: at SDH data receiving side, the received data is firstly buffered into the on-chip RAM corresponding to the SDH channel; when the buffered data can meet the quantity of once data burst written-in, the SDH data receiving side sends the request for accessing the out-chip RAM, and selects a channel, having access request, whose in-chip RAM has highest data quantity as the channel with highest priority to get the access right to the out-chip RAM.

Description

technical field [0001] The invention belongs to the field of microelectronics and relates to digital integrated circuit design technology, SDH and Ethernet technology. Background technique [0002] SDH is the English abbreviation of Synchronous Digital Hierarchy, which is the optical synchronous digital transmission network. Ethernet is a local area network that uses a shared access scheme called carrier sense multiple access / collision detection. The digitized data is loaded into the virtual container of SDH for transmission via optical fiber. The data transmission rate varies depending on the size of the virtual container. The transmission rate is as small as 1.664Mbit / s or 2.240Mbit / s, as large as 150.336Mbit / s or even higher s speed. [0003] The mainstream rate of Ethernet currently in use is 100Mbit / s or 1000Mbit / s, and the rate of some earlier devices is 10Mbit / s. The data transmission rates of the two are different, and a store-and-forward mechanism is obviously ne...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L29/02H04J3/16H04Q7/30
Inventor 姚炜白文翔
Owner CHIPHOMER TECH SHANGHAI
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