Method of reducing clock differential in a data processing system

Abstract

A method of preventing buffer underrun and buffer overrun errors in a data processing system is disclosed. The method includes providing a reference frequency for the data processing system, storing data samples to be processed in a first in, first out (FIFO) register, detecting a level of the FIFO register for indicating how many data samples are stored in the FIFO register, dividing the reference frequency by a divisor for producing a working frequency having a lower frequency than the reference frequency, wherein the divisor is not equal to zero and the divisor is adjusted according to the level of the FIFO register, and processing the data samples stored in the FIFO register using the working frequency.

Description

technical field [0001] The invention relates to a method for avoiding buffer shortage or overflow, in particular to a method for avoiding buffer shortage or overflow in a data processing system. Background technique [0002] A method for processing data in a synchronous data transmission system is that the transmitter receives a continuous analog signal and converts it into a digital signal, and transmits the digital signal to the receiver. During this process, the operating frequency of the transmitter and the operating frequency of the receiver should be Try to be the same, because there is only a small error in the operating frequency of the transmitter and receiver, which will cause abnormal operation or data loss. [0003] Please refer to Figure 1. FIG. 1 is a functional block diagram of a data transmission system 10 in the prior art. The data transmission system 10 includes a transmitting end 20 and a receiving end 30 . The transmission end 20 includes an analog / dig...

AI Technical Summary

Problems solved by technology

If b>a, the frequency of the receiving end 30 will be faster than the frequency of the transmitting end 20, causing the samples of the first-in-first-out register 28 of the receiving end 30 to be cleared after a period of time, but the transmitting end 20 has no time to generate new samples, so a Insufficient buffer situation

On the other hand, if b

[0006] Therefore, it is necessary to synchronize the frequency of the transmitting end 20 and the receiving end 30 so as not to cause buffer shortage or buffer overflow, resulting in data loss or service interruption

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