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Field programmable logical array wiring resource structure and its modeling approach thereof

A technology for programming logic and resources, applied in the direction of logic circuits using specific components, logic circuits using basic logic circuit components, etc., which can solve problems such as low resource utilization and lack of flexibility

Active Publication Date: 2009-12-30
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These connections do not pass through programmable switches and are also very fast, but they are not limited to adjacent logic cells like direct interconnects
This hard connection lacks flexibility and resource utilization is not high

Method used

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  • Field programmable logical array wiring resource structure and its modeling approach thereof
  • Field programmable logical array wiring resource structure and its modeling approach thereof
  • Field programmable logical array wiring resource structure and its modeling approach thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0030] 1. The overall structure of wiring resources

[0031] figure 1 It is the overall structure diagram of the wiring structure FPGA of the present invention. This interconnect structure FPGA is mainly composed of logic cells (CLB), programmable interconnection, unified switch matrix (GRM) and input-output unit (IOB).

[0032] The logic unit is a functional unit that implements user logic, and it usually consists of a look-up table (LUT), flip-flops, carry chains, etc.

[0033] The switch matrix can provide the exchange of horizontal wiring channels and vertical wiring channels. It has several switch types: pass transistor, driver (buffer), bidirectional driver (bidirection buffer) and metal connection (hardconnection, for turning) . The area of ​​the transmission tube is small, and the speed is fast when there are not many cascades. It is suitable for short-term connection, but the speed drops rapidly when there are many cascades; the driver can amplify and restore the s...

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PUM

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Abstract

The invention belongs to programmable component structure technology field, specially a local programmable logic array wiring resource structure and modeling method which supports the crutch line. The wiring resource structure of the invention includes: programmable interconnected line, uniform switch matrix, input and output multi path selector array and logic unit. It breaks the limit of level and uprightness interlinkage resource, introduces the concept of crutch line, makes the wiring path not pass the programmable switch, it gives attention to speed and agility. The description of wiring line resource, the interconnected line is distributed to the repeated unit then integral interconnected resource is described by describing an interconnected line resource in a repeated unit. This describing method is very flexible, the kind, amount, proportion of interconnected resource can be changed conveniently, and any switch array can be generated.

Description

technical field [0001] The invention belongs to the technical field of programmable device structures, and in particular relates to a programmable device wiring resource structure and a modeling method thereof. Background technique [0002] A field programmable logic device (FPGA) consists of a programmable logic block (CLB) and a programmable interconnect, and the programmable logic block is connected through a programmable interconnect. Traditional programmable interconnection resources are usually composed of horizontal interconnection resources and vertical interconnection resources, which are connected to each other through a switch matrix. As the scale and complexity of FPGAs become larger and larger, the speed and performance requirements of FPGAs are also getting higher and higher, and traditional interconnect resources have become the bottleneck of speed improvement. This is because the traditional interconnection structure divides interconnection resources into ho...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/177
Inventor 来金梅陈利光童家榕
Owner FUDAN UNIV
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