Phase-locking loop with frequency-control sensitivity compensation ability

Abstract

The invention provides a phase-locked loop. Using a loop bandwidth value of the phase-locked loop as a function of a phase detector gain value and a voltage-controlled oscillator gain value (or called frequency control sensitivity), by adjusting the phase detector gain value, The variation of the gain value of the voltage controlled oscillator is compensated, so that the bandwidth value of the loop is more stable.

Description

technical field [0001] The present invention relates to a phase-locked loop (Phase-Locked Loop, PLL), in particular to a PLL capable of compensating frequency control sensitivity (Tuning Sensitivity), so as to obtain a more stable loop bandwidth (Loop Bandwidth). Background technique [0002] In a communication system, a PLL is a device used to generate an output signal with a specific phase and a specific frequency, and for this purpose, the loop bandwidth W of the PLL should be maintained as much as possible within the frequency range of the PLL input signal of interest smooth. [0003] Please refer to figure 1 , which shows a system block diagram of a conventional PLL 10 . The conventional PLL 10 includes a phase detector (Phase Detector) 12 , a loop filter (Loop Filter) 14 , a voltage controlled oscillator (Voltage Controlled Oscillator, VCO) 16 , and a frequency converter (Frequency Converter) 18 . The phase detector 12 simultaneously receives an input frequency f I...

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Problems solved by technology

However, when the PLL system is integrated into an integrated circuit (Integrated Circuit, IC), it is found that the VCO gain value K VCO The linearity is severely affected, causing the control signal V at the frequency of interest t range, the VCO gain value K VCO (like figure 2 shown) cannot be approximated to a certain value, at this time, even if the phase detector gain value K PD have good linearity (such as image 3 shown), the loop bandwidth W will still be affected by the VCO gain value K VCO characteristics, resulting in a decrease in the smoothness of the loop bandwidth value W, such as Figure 4 shown, causing the control signal V at the frequency of interest t The range of the loop bandwidth W value within the range is too large

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