System and method for dynamic mirror-bank addressing

Abstract

A dynamic addressing technique mirrors data across multiple banks of a memory resource. Information stored in the memory banks is organized into separately addressable blocks, and memory addresses include a mirror flag. To write information mirrored across two memory banks, a processor issues a single write transaction with the mirror flag asserted. A memory controller detects that the mirror flag is asserted and, in response, waits for both memory banks to become available. At that point, the memory controller causes the write to be performed at both banks. To read data that has been mirrored across two memory banks, the processor issues a read with the mirror flag asserted. The memory controller checks the availability of both banks having the desired information. If either bank is available, the read request is accepted and the desired data is retrieved from the available bank and returned to the processor.

Description

technical field [0001] The present invention relates to computer systems, and more particularly, to mirroring data between multiple memory resources, such as memory banks. Background technique [0002] High performance computer systems often utilize multiple processors or central processing units (CPUs). Each processor has access to shared and personal data, such as program instructions such as algorithms, and data stored in memory coupled to the processor. A more common multiprocessor architecture is known as a systolic array, in which each processor is coupled to its nearest neighbors in a grid-like topology, and the processors perform sequences of operations on the data flowing between them . Generally, the processors of a systolic array operate in a "lock-step" fashion, where each processor alternates between a computation phase and a communication phase. [0003] Systolic arrays are typically used when the problem to be solved can be partitioned into discrete units o...

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