Damage-free switching method for main and spare synchronous digital series device timing source

Abstract

A harmless switching method for SETS function modules in a SDH system includes: mutually sending clock and frame location pulse between master and alternative modules for controlling state signals to control the one-from-two logic circuit to make the phase and frequency of the output system clocks and system frame location pulses of the two modules completely the same, each own voltage-control oscillator traces the same timing source. A returned button is set in them for controlling the alternative turning to the master by triggering it manually and the original master module is activated to realize switching. The alternative module output clock and the frame timing pulse are at ordinary output state not controlled by three states output. The module switch time scale is selected in the sphere of frame head so that the frame location pulse is continuous and a line interface module processes the clock sent by the master, alternative timing souses function module smoothly after one-from-two logic circuit.

Description

technical field [0001] The present invention relates to a method for providing a stable timing signal in a Synchronous Digital Hierarchy (SDH) system, in particular to a Synchronous Digital Hierarchy Timing Source (SETS) functional module (or other modules comprising such modules) in a Synchronous Digital Hierarchy (SDH) system ) method for lossless switching. Background technique [0002] For the normal operation of the SDH system, two synchronous digital series timing source modules (SETS) are generally provided in the system, one of which is used as the main module and the other is used as the backup module, and the main module and the backup module are mutually backup. During the working process of the SDH system, once the SETS main module fails, the system will start the standby module in the hot backup state to realize the automatic switching of the main and standby modules. When system maintenance is required, or when the maintenance personnel are upgrading the softw...

AI Technical Summary

Problems solved by technology

However, at the same time, the following problems arise: the scalability is limited; due to the wide bandwidth of the analog phase-locked loop, the noise generated by the previous digital phase-locked loop cannot be suppressed, and the clock output on the chip needs to be debounced, which not only affects the PCB The layout and routing requirements are relatively high, and it is a big improvement in cost

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