System and method for running test and redundancy analysis in parallel

Abstract

A memory redundancy analyzing apparatus having a tester, a queue, and a redundancy analyzer is provided. The tester includes testing portions for different types of fails, and each of the testing portions performs multiple tests on the memory locations and outputs fail information for at least a part of the memory device. The queue stores the fail information. The redundancy analyzer processes the fails using the fail information and produces a plurality of repair solutions. The types of fails include must fails and sparse fails. The fail information is transmitted to the queue, and the fail information includes at least a part of the fail information for the entire memory device. The tester can operate asynchronously from the redundancy analyzer.

Description

BACKGROUND[0001]1. Field of the Invention[0002]One embodiment generally relates to test of memory devices. In particular, one embodiment relates to systems and methods of repairing memory devices.[0003]2. Description of the Related Art[0004]Semiconductor memory devices can be found in a wide variety of electronics devices. Modern memory devices are relatively large in size and relatively inexpensive. A memory device typically includes at least one array of memory cells arranged in rows and columns. In a relatively large array, it can be expected that some cells will not be usable. Accordingly, redundant rows and columns exist to repair the defective cells via redundancy analysis. Tests are performed on memory devices to identify the cells that need to be replaced. For relatively large arrays, these tests comprising test patterns can be time-consuming and relatively expensive. For example, many test patterns may be run to test for gross failures, and to test for margin such as voltag...

AI Technical Summary

Problems solved by technology

In a relatively large array, it can be expected that some cells will not be usable.

For relatively large arrays, these tests comprising test patterns can be time-consuming and relatively expensive.

When the step S970 waits for completion of the step S950, the test as a whole runs slower than the speed at which the ATE can perform the test patterns, which adds time and cost to the DUT.

Images