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Methods and apparatus for cycle time improvements for atomic layer deposition

Inactive Publication Date: 2005-01-27
AIXTRON INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

In still further embodiments, the present invention allows for performing, within a half cycle, an expose period of an ALD process using a first purge flow defined in part by a first conductance of an annular gas flow pathway within the reactor chamber, and performing a purge period of the ALD process using a second purge flow greater than the first purge flow, the second

Problems solved by technology

However, given conventional ALD reactor designs (which utilize constant purge gas flow rates and strive to maintain constant reactor chamber pressures using a downstream throttle valve), this would tend to increase the required precursor exposure time.
Both the Shatas and Sneh systems for providing bi- or multi-level flows suffer from deficiencies.
These components are limited in their speed of response and also require ancillary flow (dumping) of the neutral purge gas during the period when the source is not injected into the reactor.
This makes for relatively inefficient use of purge gas.
This tends to waste purge gas.

Method used

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  • Methods and apparatus for cycle time improvements for atomic layer deposition

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Embodiment Construction

Described herein are methods and systems for cycle time improvements in ALD processes. In various embodiments, the present invention provides multi-level flow sources using pressure controlled and / or passive conductance components combined with a dual (or, more generally multiple) pump (or dual or multiple pump capacity) arrangement. Unlike the multi-level flow systems described above, in the present invention a high purge flow does not have to flow during the exposure pulse, resulting in more economical operation with respect to consumables usage. Both lower cost and better dynamic time-dependent performance is obtained, in some embodiments, by the use of pressure controlled components instead of mass flow controllers. Further, in some embodiments the use of an independent, direct-coupled conduit for neutral gas flow, instead of a purge bypass, provides multi-level purge source capability without the need for continual operation of a high purge flow.

In addition to reduced consum...

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Abstract

Different periods of an ALD cycle are performed using different purge flows and, in some cases, different pumping capacities, while maintaining the reactor chamber at a nominally constant pressure. The purge flows may, in some cases, utilize different gasses and / or may be provided through different flow paths. These operations provide for ALD cycle time improvements and economical operation with respect to consumables usage. In some embodiments the use of an annular throttle valve provides a means for controlling downstream flow limiting conductances in a gas flow path from the reactor chamber.

Description

FIELD OF THE INVENTION The present invention relates to thin film processing and, more particularly, to methods and apparatus for improvement in the cycle time of Atomic Layer Deposition (ALD) processes. BACKGROUND In the field of material deposition, a process known as atomic layer deposition (ALD) has emerged as a promising candidate to extend the abilities of chemical vapor deposition (CVD) techniques. Generally ALD is a process wherein conventional CVD processes are divided into individual, sequential deposition steps that theoretically achieve saturation (and exhibit self-limited growth) at the level of a single molecular or atomic layer thickness. After each deposition step, unreacted chemical precursors used therein (and the unwanted byproducts of the reaction) must be removed from the reactor chamber. Existing techniques for doing so include the so-called “pump” or “evacuation” method and the “purge” or “flow” method. Of these, the purge or flow procedures have become the ...

Claims

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Application Information

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IPC IPC(8): C23C16/44C23C16/455C23F1/00C30B25/14
CPCC23C16/4412C23C16/45527C30B25/14C23C16/45557C23C16/45544C23C16/455
Inventor LIU, XINYESEIDEL, THOMAS E.LEE, EDWARDDOERING, KENRAMANATHAN, SASANGAN
Owner AIXTRON INC
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