A three-dimensional wafer stacking structure with post-and-beam construction and method to stack three-dimensional wafer

Abstract

The provided wafer static structure comprises: the first wafers with multiple metal support structures, and the second wafer on top of the first wafer. Wherein, the said support structure is set on chip position to extend from the silicon surface of the first chip to the second wafer base and form a support force for preventing the damage from vertical stress or shearing stress.

Description

technical field [0001] The invention relates to a three-dimensional wafer stacking structure and a three-dimensional wafer stacking method, in particular to a three-dimensional wafer stacking structure including a metal support structure between two silicon substrates and a three-dimensional wafer stacking method. Background technique [0002] With the development of electronic manufacturing technology, more and more electronic products are developed with portability, high functionality, light weight and small size as their development goals. However, under such a development trend, the functionality of the electronic chips used in electronic products and the circuit devices contained in them will inevitably increase and become more and more complex. Under the demand for miniaturized chip areas, Although the current lithographic process of wafer manufacturing is still evolving to 45nm, 32nm and even smaller sizes; however, in any case, major changes in chip design in the fut...

AI Technical Summary

Problems solved by technology

[0004] Although the above-mentioned wafer stack structure 100' can repeatedly stack multiple wafers depending on the needs of the chip design, however, in the case of more and more wafer stack structures and more and more complex circuit device configurations, there are various device layers. The low dielectric (low-k) material in the chip is likely to be damaged due to the compressive stress of the stack structure or the thermal stress generated during circuit operation, thereby causing damage to the entire chip circuit

[0005] Although the above-mentioned chip stack structure 100' has a signal channel structure connecting different chips, these signal channels are not directly configured on the two hard surfaces of the device layer, so that the device layer cannot be generated. The effect of support

Therefore, the chip stack structure cannot avoid the damage of the low dielectric material in the device layer due to stress

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