Semiconductor device

A semiconductor and device technology, applied in the field of high withstand voltage of semiconductor devices, can solve problems such as the destruction of semiconductor devices 101, and achieve the effects of high withstand voltage and high damage tolerance

Inactive Publication Date: 2007-03-28
SHINDENGEN ELECTRIC MFG CO LTD
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

[0023] Since the protection region 146b is placed at a drift potential, in the case of an avalanche breakdown in the withstand voltage region, the current flowing due to the avalanche breakdown concentrates on the periphery of the base diffusion region 117 close to the innermost protection region 146b , the semiconductor device 101 is destroyed

Method used

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Embodiment Construction

[0103] In the present invention, either one of the P-type and N-type is referred to as the first conductivity type, and the other is described as the second conductivity type. When the first conductivity type is N-type, the second conductivity type is P-type. Conversely, when the first conductivity type is P-type, the second conductivity type is N-type.

[0104] In addition, in the following embodiments, the semiconductor substrate and the semiconductor layer are silicon single crystals, but they may be crystals of other semiconductor materials.

[0105] The structure of the semiconductor device of the present invention will now be described. Reference numeral 1 in FIGS. 27 and 28 denotes a semiconductor device according to a first example of the present invention.

[0106] First, the growth layer 12 of the first conductivity type is formed by epitaxial growth on the surface of the semiconductor support layer 11 of the first conductivity type in the wafer state. A plurality ...

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Abstract

A semiconductor device having a high withstand voltage is provided. An activation groove (22a) is composed of a long and narrow main groove part (26) and a sub-groove part (27) which is connected with a side plane in a longitudinal direction of the main groove part. On a bottom plane of the main groove part (26), a second conductivity type embedding region (24) having a height lower than a bottom plane of a second conductivity type base diffusion region (32a) is arranged, and in the sub-groove part (27), a second conductivity type activation groove filling region (25) contacting the base diffusion region (32a) is arranged. The embedding region (24) is brought into contact with the base diffusion region (32a) through the activation groove filling region (25). In the one activation groove (22a), since one gate groove (83) is formed at a part upper than the embedding region (24), a gate electrode plug (48) is not interrupted and an electrode pattern is simplified.

Description

technical field [0001] The present invention relates to a technique for increasing the withstand voltage of a semiconductor device, and particularly relates to a technique for increasing the breakdown resistance while increasing the withstand voltage. Background technique [0002] In the technical field of power semiconductor devices, devices with a reduced surface electric field (RESURF) structure have been studied as a powerful means for increasing withstand voltage. [0003] Reference numeral 101 in FIG. 38 is an example of a MOSFET type semiconductor device, and an N-type resistance layer 112 having a large resistance value is formed by epitaxial growth on an N-type substrate 111 having a small resistance value. [0004] On the inner surface of the resistance layer 112, a plurality of P-type guard regions 146b having a planar shape of a square ring are concentrically formed. [0005] In the area surrounded by the innermost protection area 146b, a plurality of P-type and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/28H01L29/423H01L29/47H01L29/49H01L29/872H01L29/06H01L29/08H01L29/739
CPCH01L29/0878H01L29/66712H01L29/1095H01L29/7809H01L29/7802H01L29/7395H01L29/0619H01L29/7811H01L29/47H01L29/0696H01L29/0634H01L2924/0002H01L2924/00H01L29/0646
Inventor 九里伸治宍户宽明三川雅人大岛宏介栗山昌弘北田瑞枝
Owner SHINDENGEN ELECTRIC MFG CO LTD
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