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Clock, signal multiplex method and system

A clock and signaling technology, applied in the field of signaling multiplexing method and system, and clock, can solve problems such as high cost and complex system design, achieve the effect of reducing implementation cost, reducing interface resources, and improving scalability

Inactive Publication Date: 2006-04-12
HUAWEI TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007]Another object of the present invention is to provide a clock and signaling multiplexing system to overcome the shortcomings of complex system design and high cost in the prior art to reduce system design costs and improve system scalability

Method used

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  • Clock, signal multiplex method and system
  • Clock, signal multiplex method and system
  • Clock, signal multiplex method and system

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0087] In this example,

[0088] The master clock board 60 includes: a clock source module 601 for generating a reference frequency source; a timing information generation module 602 for generating system timing information; a simplex signaling generation module 603 for generating system simplex signaling.

[0089] In addition, the main control clock board 60 also includes:

[0090] The encoding module 604 is respectively coupled to the clock source module, the timing information generation module and the simplex signaling generation module, and is used to multiplex the reference frequency source, system timing information and simplex signaling into a serial data stream output;

[0091] The output interface module 605 is coupled to the encoding module 604, and is used to output the serial data stream to the service board through the physical bus L1.

[0092] Service single board 61 includes:

[0093] An input interface module 615 for receiving the serial data stream input by...

no. 2 example

[0097] In order to make the encoding strictly synchronized with the system clock when the system timing information and simplex signaling are encoded, in this embodiment, an encoding phase-locked loop module 606 is connected between the clock source module 601 and the encoding module 604, through This module ensures that the frequency of the serial data stream output by the encoding module is consistent with the frequency of the reference frequency source generated by the clock source module.

[0098] Similarly, on the service board, in order to obtain the frequency required by the service board strictly synchronized with the system from the input serial data stream, so as to ensure that each service board works synchronously with the system. A frequency recovery module 616 is connected between the input interface module 615 and the decoding PLL module 611 . Since the serial data stream output by the input interface module contains system timing and signaling information, the ...

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Abstract

A method for multiplexing clock and signaling includes generating reference frequency source information, system timing information and simplex signaling by main control clock board, multiplexing said information and signaling to be a serial data stream being transmitted on each service signal board, obtaining required information by each service single board according to serial data stream. The system for realizing the method consists of main control clock board, at least one service board, at least one physical bus for connecting said clock board to said service board.

Description

technical field [0001] The invention relates to the technical field of communications, in particular to a clock and signaling multiplexing method and system. Background technique [0002] At present, most communication devices adopt a distributed system structure. The advantage of a distributed system structure is that different functions can be easily allocated to different boards, which facilitates modular design and debugging during development. There is usually a core control unit that controls the operation of the entire system through signaling interaction. At the same time, each sub-module in the system is required to work at a strictly unified clock frequency and system time as a whole. Therefore, there is usually a core system clock that generates the frequency source and system time. Among them, the frequency source is distributed to each service board as the reference input of the local phase-locked loop of each board to generate various clocks that lock the sys...

Claims

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Application Information

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IPC IPC(8): H04L5/02
CPCH04J3/0685H04L7/0008
Inventor 蒋亚军
Owner HUAWEI TECH CO LTD
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