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Electric erasing programmable logic element

A programming logic and electric erasing technology, which is applied to electrical components, electrical solid-state devices, circuits, etc., can solve the problem of large area of ​​single-layer polysilicon storage cells

Inactive Publication Date: 2004-06-16
EMEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] Therefore, the main purpose of the present invention is to provide an electrically erasable programmable logic element, which uses single-layer polysilicon technology, includes a floating gate and a floating ion-doped region, and is used to store data to solve the problem of The above-mentioned problem that the area of ​​the existing single-layer polysilicon storage unit is too large

Method used

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  • Electric erasing programmable logic element
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Embodiment Construction

[0022] see figure 2 , figure 2 A front sectional view of an Electrically Erasable Programmable Logic Device (Electrically Erasable Programmable Logic Device) 50 of the present invention is shown in FIG. The electrically erasable programmable logic element 50 includes a P-type substrate (P-Type Substrate) 52; a first N-type ion-doped region 54, located in the P-type substrate 52; a first gate 56, which Located above the P-type substrate 52 and adjacent to the first N-type ion-doped region 54, and in a floating (Floating) state, used as a floating gate of the electrically erasable programmable logic element 50 to store The nonvolatile data of the electrically erasable programmable logic element 50; a second N-type ion-doped region 58a, located in the P-type substrate 52 and adjacent to the first grid 56; a third N-type The ion-doped region 58b is located in the P-type substrate 52 and is electrically connected to the second N-type ion-doped region 58b; a second gate 60, whic...

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Abstract

The invention discloses an electrically erasable programmable logic element, containing a P-substrate; a first N-ion impurity region in the P-substrate; a first grid on the P-substrate, adjacent to the first N-ion impurity region, and in a floating state, storing data; a second N-ion impurity region in the P-substrate and adjacent to the first grid; a second grid as a control one, situated on the P-substrate and adjacent to the second N-ion impurity region; a third N-ion impurity region in the P-substrate and adjacent to the second grid.

Description

technical field [0001] The invention relates to an electrically erasable programmable logic element, in particular to an electrically erasable programmable logic element which can be manufactured by using a standard CMOS process, and does not require additional floating gate area to reduce volume. Background technique [0002] In recent years, as the demand for portable electronic products increases, the technology and market application of Electrically Erasable Programmable Read-Only Memory (hereinafter referred to as EEPROM) are becoming increasingly mature and expanding. The fields of application of EEPROM include products such as negatives of digital cameras, mobile phones, video game consoles (Video Game Console), memory cards of personal digital assistants (Personal Dieital Assistant, PDA), telephone answering devices, and programmable ICs. EEPROM is a kind of non-volatile memory (Non-Volatile Memory). Its operating principle is to control the opening or closing of the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H10B69/00
Inventor 李昆鸿徐清祥金雅琴沈士杰何明洲
Owner EMEMORY TECH INC
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