Formation of pulse signal from clock signal

Abstract

Providing technology capable of satisfying a request value concerning the specified period of a pulse signal, without excessively lowering the cycle of a clock signal, even if considering fluctuation in delay time is taken into consideration, in a delay element. Two first delay signals Q30 and Q34 are generated such that edges thereof are delayed by a first delay time Td1 in relation to the rising edge of a clock signal CLK. Two second delay signals Q32 and Q36 are also generated such that edges thereof are delayed by a second delay time Td2 in relation to the trailing edge of the clock signal CLK. A pulse signal Sout is generated as a result of logic operations performed on the first delay signals Q30 and Q34 and the second delayed signals Q32 and Q36.

Description

technical field [0001] The present invention relates to a technique for generating a specific pulse signal from a clock signal of a certain period. Background technique [0002] Figure 13 It is a block diagram showing an example of a conventional pulse signal generating circuit 200 for generating a specific pulse signal Q230 from a clock signal CLK. This circuit 200 includes a D flip-flop 210 (hereinafter referred to as "DFF 210"), two delay elements 220 and 222 connected in series, and a NAND gate 230 with one of the two input terminals serving as an inverting input terminal. A clock signal CLK is supplied to a clock input terminal of DFF 210 . The output Q210 of the DFF 210 is input to the first delay element 220, and the inverted output #Q210 is fed back to the D input terminal. The delay signal Q220 delayed by the first delay element 220 is input to the non-inverting input terminal of the NAND gate 230 . In addition, the delayed signal Q220 is input to the inverting ...

AI Technical Summary

Problems solved by technology

[0014] In this way, in the conventional pulse signal generation circuit, in order to satisfy the required value for a specific period of the pulse signal, there is a problem that the cycle of the clock signal must be greatly reduced in consideration of the fluctuation of the delay time in the delay element.

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