High-speed dynamic comparator with metastable state suppression technology

A technology of dynamic comparator and metastable state, applied in multiple input and output pulse circuits, etc., can solve the problems affecting the accuracy of SARADC, comparator metastable state, wrong comparison results, etc., achieve simple structure, improve comparison speed, Effect of Power Consumption Reduction

Pending Publication Date: 2021-07-13
SOUTHEAST UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the existing research, several comparators suitable for high-speed ADCs have also been proposed. However, as the input signal amplitude decreases, the delay of the comparator becomes larger. At the same time, with the continuous improvement of the SARA

Method used

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  • High-speed dynamic comparator with metastable state suppression technology
  • High-speed dynamic comparator with metastable state suppression technology
  • High-speed dynamic comparator with metastable state suppression technology

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Embodiment Construction

[0031] The present invention will be further described below in conjunction with the accompanying drawings.

[0032] Such as figure 1 Shown, a kind of high-speed dynamic comparator with metastability suppression technology of the present invention comprises pre-amplifier 1, post-stage latch 2 and metastable state suppression circuit 3; Preamplifier 1 realizes to input differential signal namely The positive terminal input signal VIP and the negative terminal input signal VIN are amplified, and the output amplifier positive terminal output signal P and the amplifier negative terminal output signal N are connected to the two input terminals of the subsequent stage latch 2; the latter stage latch 2 realizes the input Fast comparison of the signals, the output signal VOP at the positive end of the latch and the output signal VON at the negative end of the latch are sent to the metastable suppression circuit 3; the output clock signal CLK of the metastable suppression circuit 3 is co...

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Abstract

The invention discloses a high-speed dynamic comparator with a metastable state suppression technology. The high-speed dynamic comparator comprises a pre-amplifier, a post-latch and a metastable state suppression circuit, the pre-stage amplifier amplifies an input differential signal, drains of a first PMOS tube and a second PMOS tube of the pre-stage amplifier are connected with the post-stage latch, the positive feedback characteristic of the latch is utilized, a pull-down NMOS tube and a pull-up PMOS tube are added, and pull-up or pull-down of an amplifier positive end output signal and an amplifier negative end output signal is completed. And a relatively high comparison speed is realized. And after comparison is completed, the tail current tube is quickly turned off, so that the comparator has no static power consumption, and the power consumption of the comparator is effectively reduced. The invention adopts a metastable state suppression technology, effectively suppresses the metastable state of the comparator without introducing obvious delay, and does not obviously increase the comparison time of the comparator.

Description

technical field [0001] The invention relates to a high-speed dynamic comparator with metastable suppression technology, and belongs to the technical field of comparators in high-speed analog-to-digital converter structures. Background technique [0002] With the rapid development of portable devices, the demand for medium-resolution high-speed Analog-to-Digital Converters (Analog-to-Digital Converters, ADCs) in the fields of communication, digital imaging, and audio systems continues to increase. The sampling rate of the medium-resolution (8-10 bits) single-channel successive approximation (Successive Approximation Register, SAR) ADC based on advanced technology can reach tens or even hundreds of MHz. The interleaved SARADC can increase the speed of the ADC, but there are still problems such as multiple comparator offsets and multi-channel mismatch. In the case of high-speed sampling and small input signal amplitude, the comparator is required to have high resolution and hi...

Claims

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Application Information

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IPC IPC(8): H03K5/24
CPCH03K5/24Y02D10/00
Inventor 吴建辉阚佳慧李红
Owner SOUTHEAST UNIV
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