PCIE link stability test method and device, computer equipment and medium

Abstract

The invention relates to a PCIE link stability test method and device, computer equipment and a storage medium, and relates to the technical field of computer application. The method comprises the following steps: constructing a GPU communication ring according to a topological structure of a GPU in a PCIE link to be tested; sending a test instruction to a target GPU in the GPU communication ring,controlling the target GPU to generate a test data block according to the size of the test data block in the test instruction, and controlling each GPU included in the GPU communication ring to sequentially transmit the test data block; and in the process of transmitting the test data block, obtaining state data of each GPU included in the GPU communication ring, and determining a test result ofthe PCIE link to be tested according to each state data. According to the embodiment of the invention, all communication nodes on the to-be-tested PCIE link are connected based on the GPU communication ring, and the GPU included in the GPU communication ring is controlled to sequentially transmit the test data blocks to achieve overall pressurization of the to-be-tested PCIE link, so that the overall performance of the PCIE link can be tested, and the test result can better reflect the overall performance of the to-be-tested PCIE link.

Description

technical field [0001] The present application relates to the field of computer application technology, in particular to a stability test method, device, computer equipment and media of a PCIE link. Background technique [0002] In deep learning training, multiple GPU parallel training methods are often used for network training. As the complexity of deep learning networks increases, more and more GPUs are required for network training. However, due to the limited number of channels on the CPU, the number of GPUs that can be directly connected to the CPU is limited. For this reason, a solution of connecting a PCIE switch chip to the CPU and then connecting multiple GPUs to the PCIE switch chip is currently proposed. Among them, a link composed of a CPU, a PCIE switch chip, and multiple GPUs is called a PCIE link. In practical applications, after the PCIE link is constructed, it is necessary to perform a stress test on the PCIE link to detect the performance of the PCIE li...

AI Technical Summary

Problems solved by technology

[0004] However, the above test results for each individual link cannot accurately reflect the overall performance of the PCIE link

Images