Method for forming channel hole of three-dimensional memory device, and three-dimensional memory device

Abstract

The present invention relates to a method for forming a channel hole of a three-dimensional memory device. The method comprises the steps: providing a substrate, a stacking layer located on the substrate and a dielectric layer covering the stacking layer, wherein the stacking layer comprises a plurality of insulating layers and a plurality of dummy gate layers which are stacked alternately; forming virtual channel holes penetrating through the dielectric layer and the stacking layer, wherein the virtual channel hole reaches the substrate; and respectively filling the virtual channel holes witha plurality of materials, wherein the plurality of materials have different hardness.

Description

technical field [0001] The present invention relates to semiconductor manufacturing, and in particular to methods for forming channel holes for three-dimensional memory devices and three-dimensional memory devices. Background technique [0002] In order to overcome the limitation of the two-dimensional memory, the industry has developed a memory having a three-dimensional (3D) structure, which improves integration density by three-dimensionally arranging memory cells on a substrate. [0003] Furthermore, in a three-dimensional memory such as 3D NAND flash memory, the memory array may include a core area and a step area. The step area is used to lead out the contact portion of the control gate in each layer of the memory array as a word line connection area. These control gates are used as word lines of the memory array to perform operations such as programming, erasing and writing, and reading. In the manufacturing process of 3D NAND flash memory, contact holes are formed ...

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Problems solved by technology

Both of these situations will adversely affect the subsequent process and the performance of the final 3D memory

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